Ex Parte Rajan et al

Patent Trial and Appeal Board

Sep 30, 2016

13620650 (P.T.A.B. Sep. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/620,650 09/14/2012 Suresh Natarajan Rajan
26192 7590 10/04/2016
FISH & RICHARDSON P,C
PO BOX 1022
MINNEAPOLIS, MN 55440-1022
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
16113-1928002 1076
EXAMINER
LOONAN, ERIC T
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
10/04/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
P ATDOCTC@fr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SURESH NATARAJAN RAJAN, KEITH R. SCHAKEL,
MICHAEL JOHN SEBASTIAN SMITH, DAVID T. WANG, and
FREDERICK DANIEL WEBER
Appeal2015-001955
Application 13/620,650
Technology Center 2100
Before JAMES R. HUGHES, DAVID M. KOHUT, and
TERRENCE W. McMILLIN, Administrative Patent Judges.
HUGHES, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Decision rejecting claims 1-20, which constitute all the
claims pending in this application. See App. Br. 2. 1 We have jurisdiction
under 35 U.S.C. § 6(b ).
We affirm-in-part.
1 We refer to Appellants' Specification ("Spec.") (filed Sept. 14, 2012)
(claiming benefit of US 60/772,414 (filed Feb. 9, 2006) and US 60/865,624
(filed Nov. 13, 2006)); Appeal Brief ("App. Br,") (filed May 27, 2014); and
Reply Brief ("Reply Br.") (filed Nov. 10, 2014). We also refer to the
Examiner's Answer ("Ans.") (mailed Sept. 29, 2014), and Final Office
Action (Final Rejection) ("Final Act.") (mailed Aug. 30, 2013).
Appeal2015-001955
Application 13/620,650
Appellants 'Invention
The invention at issue on appeal concerns apparatuses, systems and
methods for controlling memory, in particular, simulating (virtualizing)
memory circuits and associating the virtual memory circuits with a set of
scheduling constraints. (Spec. i-fi-12 and 4; Abstract.)
Illustrative Claim
Independent claim 1, reproduced below with the key disputed
limitations emphasized, further illustrates the invention:
1. An apparatus comprising:
an interface circuit electrically connected to a first number
of physical dynamic random access memory ("DRAM") devices
via multiple data paths including a first data path and a distinct
second data path, wherein each of the physical DRAM devices is
an individual and independent monolithic device, the interface
circuit configured to:
communicate with the first number of physical DRAM
devices and a memory controller,
interface the first number of physical DRAM devices to
simulate a different, second number of virtual DRAM devices as
presented to the memory controller, each of the virtual DRAM
devices being simulated as an individual and independent
monolithic device,
simulate a first virtual DRAM device using a first physical
DRAM device on the first data path and a second physical
DRAM device on the distinct second data path,
use both a physical row of the first physical DRAM device
and a physical row of the second physical DRAM device to
simulate a virtual row of the first virtual DRAM device,
receive a row-access command from the memory
controller, directed to the first virtual DRAM device, for the
virtual row of the first virtual DRAM device,
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Application 13/620,650
based on the received row-access command, translate the
received row-access command for the virtual row to a first row
access command for the physical row of the first physical DRAM
device and a second row access command for the physical row
of the second physical DRAM device, and
issue the first row access command and the second row
access command to activate the physical row of the first physical
DRAM device and the physical row of the second physical
DRAM device, respectively, before a subsequent column-access
command is received from the memory controller to access a part
of the simulated row that corresponds to the physical row of the
first physical DRAM device or the physical row of the second
physical DRAM device.
App. Br. 26 and 27 (Claims Appendix).
Rejections on Appeal
1. The Examiner provisionally rejects claims 1-8, 10-14, and 16-
20 on the ground of non-statutory obviousness-type double patenting over
the corresponding claims of co-pending application US 11/672,924 ("'924
A.. .,.,,
App. J.
2. The Examiner rejects claims 1-20 under 35 U.S.C. § 103(a) as
being unpatentable over Ruckerbauer et al. (US 2006/0129740 Al;
published June 15, 2006 (filed Dec. 13, 2004)) ("Ruckerbauer"), Lee et al.
(US 6,262,93 8 B 1, issued July 1 7, 2001) ("Lee"), and Manton et al. (US
4,500,958, issued Feb. 19, 1985) ("Manton")
RELATED APPEAL
Appellants indicate that an Appeal Brief was filed for a related patent
application, U.S. Patent Application No. 11/672,921, January 24, 2014.
App. Br. 1. The appeal has been assigned Appeal No. 2014-006763. The
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Appeal2015-001955
Application 13/620,650
Board has not issued a decision on Appeal No. 2014-006763. Appellants
indicate that an Appeal Brief was filed for a related patent application, U.S.
Patent Application No. 11/929,225, January 24, 2014. App. Br. 1. The
appeal has been assigned Appeal No. 2014-006782. The Board has not
issued a decision on Appeal No. 2014-006782. We note that related patent
application, U.S. Patent Application No. 11/672,924 is also the subject of an
Appeal to the Board. The appeal has been assigned Appeal No. 2015-
004751. The Board has not issued a decision on Appeal No. 2015-004751.
ISSUES
Based upon our review of the administrative record, Appellants'
contentions, and the Examiner's findings and conclusions, the pivotal issues
before us are as follows:
1. Does the Examiner err in rejecting claims 1-8, 10-14, and 16-
20 on the ground of non-statutory obviousness-type double patenting over
the corresponding claims of the '924 Application.
2. Does the Examiner err in finding that the combination of
Ruckerbauer, Lee, and Manton collectively would have taught or suggested
"an interface circuit configured to" "interface the first number of physical
DRAM devices to simulate a different, second number of virtual DRAM
devices," within the meaning of Appellants' claim 1 and the commensurate
limitations of claims 10 and 16?
ANALYSIS
The Double Patenting Rejection
Appellants do not address the Examiner's findings with respect to the
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Application 13/620,650
co-pending application (the '924 Application). See App. Br. 6; see
generally, App. Br. 6-26; Reply Br. 1-13. Accordingly, we summarily
affirm the Examiner's provisional non-statutory obviousness-type double
patenting rejection of claims 1-8, 10-14, and 16-20.
The § 103 Rejection
Appellants contend that Ruckerbauer does not teach the disputed
limitation of claim 1 because Ruckerbauer does not describe an interface
circuit configured to interface a number of physical DRAM devices to
simulate a different, second number of virtual DRAM devices. See App. Br.
11-15; Reply Br. 1--4. Specifically Appellants contend that "[t]here is no
virtualization of memory devices disclosed in the cited portion of
Ruckerbauer." App. Br. 13.
Appellants persuade us of error in the obviousness rejection of claim
1. We have reviewed the sections of Ruckerbauer cited by the Examiner.
While Ruckerbauer generally describes multiple independent memory
devices sharing a data bus (see Final Act. 10-12; Ans. 3-5 (citing
Ruckerbauer i-fi-19, 27, 39, 41; Fig. 1), which the Examiner maintains meets
Appellants' virtualization limitation (supra), we agree with Appellants that
the Examiner does not establish these sections disclose simulating memory
circuits (i.e., virtual memory). Appellants' claim requires an interface not
only capable of simulating memory (memory circuits), but simulating a first
group (number) of memory circuits as second group of memory circuits
having a different number of memory circuits. The Examiner has not shown
that Ruckerbauer describes virtual (simulated) memory, much less the
specific simulation recited in claim 1.
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Application 13/620,650
Consequently, we are constrained by the record before us to find that
the Examiner erred in finding Ruckerbauer, Lee, and Manton teach the
disputed limitations of Appellants' claim 1. Independent claims 10 and 16
include limitations of commensurate scope. Claims 2-9, 11-15, and 17-20
depend on claims 1, 10, and 16, respectively. Accordingly, we reverse the
Examiner's obviousness rejection of claims 1-20.
CONCLUSION
Appellants have not shown that the Examiner erred in provisionally
rejecting claims 1-8, 10-14, and 16-20 on the ground of non-statutory
obviousness-type double patenting.
Appellants have shown that the Examiner erred in rejecting claims 1-
20 under 35 U.S.C. § 103(a).
DECISION
We affirm the Examiner's rejection of claims 1-8, 10-14, and 16-20
(on the ground of non-statutory obviousness-type double patenting) and
reverse the Examiner's rejection of claims 9 and 15 (under§ 103).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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