Ex Parte Rahimo et al

Patent Trial and Appeal Board

Mar 27, 2013

11812030 (P.T.A.B. Mar. 27, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MUNAF RAHIMO, ARNOST KOPTA, and
STEFAN LINDER
____________

Appeal 2010-010612
Application 11/812,030
Technology Center 2800
____________

Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM, and
ANDREW J. DILLON, Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-010612
Application 11/812,030

2
STATEMENT OF THE CASE
Appellants are appealing claims 1-11. Appeal Brief 1. We have
jurisdiction under 35 U.S.C. § 6(b) (2012).
We reverse.

Introduction
The invention is directed a method for producing a high-voltage
“power semiconductor in which particles of a first charge carrier type are
implanted into a lightly doped layer of the first charge carrier type”
implanted into a lightly doped layer of the first charge carrier type and
driven to a predetermined depth. Appeal Brief 2.

Illustrative Claim
1. A method for producing a high-voltage power
semiconductor for operation at high blocking voltages of
greater than 2000 V comprising a drift layer having a doping of
a first charge carrier type, a first stop layer having a doping of
the first charge carrier type, and an electrode of a second charge
carrier type, wherein the doping of the first stop layer is higher
than the doping of the drift layer the method for producing the
power semiconductor comprising:
proceeding from a lightly doped layer of a first charge
carrier type, a medium- doped layer is produced at one side of
the lightly doped layer to form the first stop layer, and the
remaining part of the lightly doped layer forms the drift layer;
and
indiffusing the electrode is into one of the drift layer and
first stop layer, which has the highest doping of the layers of the
first charge carrier type,
wherein after the production of the medium-doped layer
and before the production of the electrode, at a side of the
Appeal 2010-010612
Application 11/812,030

3
medium-doped layer which is remote from the lightly doped
layer, producing a highly doped layer to form a second stop
layer, wherein the doping of the highly doped layer is higher
than the doping of the medium-doped layer, and metallizations
are applied after the indiffusion of the electrode.

Rejection on Appeal
Claims 1-11 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over European Patent Application, first embodiment, Figures
1-6 (EP 1 237 200 A2) (’200) and European Patent Application, third
embodiment, Figures 8 and 9 (EP 1 237 200 A2). Answer 3-8.

Issue on Appeal
Do the first and third embodiments of the cited European Patent
Application, either alone or in combination, disclose a highly doped second
stop layer in conjunction with a first stop layer in a high voltage power
semiconductor?

ANALYSIS
The Examiner finds that the first embodiment of the cited European
Patent Application teaches the process steps claimed with the exception of
proceeding from a lightly doped drain layer of a first carrier charge type, a
medium-doped layer is produced at one side of the lightly doped layer to
form the first stop layer, and the remaining part of the lightly doped layer.
Answer 5. Examiner further finds that the third embodiment teaches the
process step that the first embodiment does not:
Nevertheless, ’200, third manufacturing method,
FIGS. 8-9.does teach the process step (b) wherein
Appeal 2010-010612
Application 11/812,030

4
proceeding from a lightly doped layer of a first charge
carrier type (n type silicon 81, FIG. 8A, [0045]), a
medium-doped layer (23, FIG. 8A, note that n buffer layer
is more heavy doped than 81 because of the phosphorus
ion implanted and heat treatment is applied, [0045]) is
produced at one side (bottom side) of the lightly doped
layer (81) to form the first stop layer (23), and the
remaining part of the lightly doped layer (remaining of
[81- 23], FIG. 8B, note that as shown in FIG. 6 of the first
embodiment wherein the n+ buffer layer is formed by a
similar method as disclosed in FIGS. 8A-8B, third
manufacturing method, therefore it would have been
obvious to combine ’200, first embodiment, FIGS. 1-6 and
’200, third manufacturing method, FIGS. 8-9 to show a
process step of forming the n dopant layer [23] in the rear
surface of the n- drift layer [21]).
Answer 5.
Appellants argue that there is “no nexus” between the first and third
embodiments of the invention disclosed in the European Patent Application
that would lead one of ordinary skill in the art to combine the two
embodiments. Appeal Brief 6.
Appellants argue that:
Concerning the first embodiment, the EP ’200 patent
discloses that when the structure is used having only the n
buffer layer and a high reverse bias is applied, the
thickness of the n buffer layer 23 is increased in an
effort to maintain the static breakdown voltage. See EP
’200, pgph 25. This structure, however, also results in an
increase in on-state voltage. The n+ buffer layer 31 is
thereby formed on the n buffer layer 23 so that the static
breakdown voltage can be maintained when a high reverse
bias is applied and without having an increase in the
thickness of the n buffer layer 23. Therefore, in the first
embodiment the n+ buffer layer 31 is used prevent the
increase in the thickness of the n buffer layer 23 and
Appeal 2010-010612
Application 11/812,030

5
thereby prevent an increase in on-state voltage of the
device.

Regarding the third manufacturing [third embodiment]
method, the EP ’200 patent discloses that this method is
designed to stabilize the film thickness after lapping. See
Id., pgph 43. By stopping the etching of oxide films 82
and 82 at the interface between the n buffer layer and the
oxide films 82 and 84, the thickness of the wafer 81 can
be maintained after etching. Id., pgph 49. Because the
thickness of the wafer can be maintained when a high
reverse bias is applied, which application would inevitably
occur after etching, there is no need to apply the n+ buffer
layer 31.

Therefore, based on the guidance provided, one of
ordinary skill would understand that the first embodiment
(as noted by the Examiner) and the third manufacturing
method [third embodiment] are two different approaches
to solving the problem of stabilizing film thickness. In
particular, the first embodiment addresses this problem by
the forming of an n+ buffer layer 31 on the rear surface of
the n buffer layer 23. In contrast, the third manufacturing
method describes a technique in which the film thickness
is stabilized through the application and etching of oxide
films on the n buffer layer 23. Accordingly, as it relates to
n+ buffer layer 31, there is no nexus between the first
embodiment of the EP ’200 patent and the third
manufacturing method [third embodiment] of the EP ’200
patent. One of ordinary skill would understand that there
is no need to form the n+ buffer layer 31 on the n buffer
layer 23 when executing the third manufacturing method
[third embodiment] since the film thickness is stabilized
through an alternative technique.

Appeal Brief 6-7.
Appeal 2010-010612
Application 11/812,030

6
We do not agree with the Examiner’s findings and we find Appellants
arguments to be persuasive. The two embodiments address the same issue in
two different manners. See European Patent Application Figures 1-6, 8, and
9. We find Appellants’ arguments that “in the first embodiment the n+
buffer layer 31 is used prevent the increase in the thickness of the n
buffer layer 23 and thereby prevent an increase in on-state voltage of the
device” while the process employed in the third embodiment allows the
thickness of the wafer to be maintained when a high reverse bias is applied
and therefore eliminates the need for the n+ buffer layer 31, to be persuasive.
Appeal Brief 6. Therefore, we reverse the Examiner’s rejection of claims 1-
11.

DECISION
The obviousness rejection of claims 1-11 is reversed.

REVERSED

llw