Ex Parte Radosavljevic et alDownload PDFPatent Trials and Appeals BoardMay 6, 201613042973 - (D) (P.T.A.B. May. 6, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/042,973 03/08/2011 45209 7590 05/10/2016 BLAKELY SOKOLOFF TAYLOR & ZAFMAN c/o CPA Global 900 2nd A venue South, Suite 600 Minneapolis, MN 55402 Marko Radosavljevic UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 42P21414C 7977 EXAMINER NADAV,ORI ART UNIT PAPER NUMBER 2811 NOTIFICATION DATE DELIVERY MODE 05/10/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): inteldocs _ docketing@cpaglobal.com Database_ Group@bstz.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MARKO RADOSA VLJEVIC, AMIAN MAJUMDAR, SUMAN DATTA, JACK KA VALIEROS BRIANS. DOYLE, JUSTIN K. BRASK, and ROBERTS. CHAU Appeal2013-000704 Application 13/042,973 Technology Center 2800 Before BRADLEY R. GARRIS, RICHARD M. LEBOVITZ, and JULIA HEANEY, Administrative Patent Judges. LEBOVITZ, Administrative Patent Judge. DECISION ON APPEAL This appeal involves claims directed to a transistor. Appellants appeal from the Examiner's final rejection of claims 1, 3-8, 10-15, 17-19, and 21- 23 as lacking a written description under 35 U.S.C. § 112, as inoperative and lacking utility under 35 U.S.C. § 101, and as obvious under 35 U.S.C. § 103. We have jurisdiction under 35 U.S.C. § 134. The Examiner's rejections under§ 112 and§ 101 are reversed. The§ 103 rejection is affirmed. Appeal2013-000704 Application 13/042,973 STATEMENT OF CASE Claims 1, 3-8, 10-15, 17-19, and 21-23 are pending and stand finally rejected by the Examiner as follows: 1. Under 35 U.S.C. § 112, first paragraph, as failing to comply with the written description requirement; 2. Under 35 U.S.C. § 101 because the disclosed invention is inoperative and therefore lacks utility; and 3. Under 35 U.S.C. § 103(a) as obvious in view of Kim (US 2004/0063286 Al, published April 1, 2004) in view of Dennard (US 7,273,785 B2, issued Sep. 25, 2007). There are four independent claims, claims 1, 8, 15, and 21. Appellants did not argue the claims separately. We therefore choose claim 1 as representative and claims 3-8, 10-15, 17-19 and 21-23 stand or fall together with claim 1. 37 C.F.R. § 41.37(c)(iv). Claim 1 is reproduced below: 1. A transistor structure, comprising: a semiconductor body disposed on an insulator layer of a substrate; source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and a gate stack comprising a gate insulation material and a conductive gate material, the gate stack disposed entirely around the channel region of the semiconductor body with a portion of the gate stack is disposed in a cavity disposed in the insulator layer of the substrate, wherein the portion of the gate stack disposed in the cavity comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material. 2 Appeal2013-000704 Application 13/042,973 1. REJECTION UNDER SECTION 112, FIRST PARAGRAPH The Examiner found that the claimed limitation "[ 1] the gate stack disposed entirely around the channel region of the semiconductor body with [2] a portion of the gate stack is disposed in a cavity disposed in the insulator layer of the substrate" as recited in claim 1 is not described in the Specification. Final Rej 'n 5 (the bracketed numerals 1 and 2 have been added for reference). The Examiner made the same findings for claims 8, 15, and 21 which have similar limitations. Id. at 6-7; Answer 3-5. The Examiner states that the "the final structure of the claimed invention is not depicted in the drawings in such a way which clearly illustrates one device comprising" the recited limitation. Answer 12-13. The Examiner's rejection is not supported by a preponderance of the evidence. The Specification describes the manufacture of the claimed transistor structure. The transistor has a silicon body 25. Spec. i-f 20, Fig. 2. The silicon body 25 has a channel region. Id. at i-f 28. Paragraphs 32 and 33 of the Specification describe making a trench 50 underneath the silicon body 25. Figs. 8 and 9 show trench 50. Id. at i-f 33. The trench 50 corresponds to the claimed "cavity." Paragraphs 34, 35, and 37 describe forming the gate dielectric and electrode - the "gate stack" of claim 1 - around the silicon body 25. Because the silicon body 25 has a channel region (id. at i-f 28), forming the gate stack around the silicon body thereby makes "[ 1] the gate stack disposed entirely around the channel region of the semiconductor body" as recited in claim 1. Fig. 10 illustrates this configuration and the legend to the figure specifically states that it is "cross-sectional, elevation 3 Appeal2013-000704 Application 13/042,973 view [which] ... illustrates the formation of the gate encircling the entire channel region of a semiconductor body." Id. at i-f 15. Paragraph 37 of the Specification describes forming the gate stack beneath the silicon body 25. Paragraph 37 refers to Fig. 9 as illustrating this step. Fig. 9 shows the gate stack in trench 50, meeting the description of "[2] a portion of the gate stack is disposed in a cavity disposed in the insulator layer of the substrate." Based on this disclosure, we conclude that the Specification reasonably conveys to a person of ordinary skill in the art that the inventors had possession of a transistor with both limitations [ 1] and [2] recited in claims 1, 8, 15, and 21. The Examiner's complaint that both limitations [1] and [2] are not shown in a single drawing is not persuasive because the Specification expressly describes a transistor with these limitations as indicated above. The figures which illustrate limitations [1] and [2] show different perspectives of the same transistor. A preponderance of the evidence establishes that the Specification satisfies the written description requirement; accordingly, the rejection of claims 1, 3-8, 10-15, 17-19, and 21-23 as lacking written description is reversed. 2. REJECTION UNDER SECTION 101 The Examiner rejected claims 1, 3-8, 10-15, 17-19, and 21-23 under 35 U.S.C. § 101 as inoperative and lacking utility because, when the "gate stack [is] disposed entirely around the channel region of the semiconductor body," the "movement of electrons/holes cannot be established inside the channel region, between the source and drain regions, because the channel 4 Appeal2013-000704 Application 13/042,973 region is separated or 'isolated' from the source and drain regions by the gate insulation material." Final Rej 'n 8. The Examiner's interpretation of "entirely around" the channel region of the semiconductor body is not reasonable when read in the context of the Specification. Claim terms are given their broadest reasonable interpretation consistent with the patent specification. In re Suitco Surface, Inc., 603 F.3d 1255, 1259 (Fed. Cir. 2010); In re Abbott Diabetes Care Inc., 696 F.3d 1142, 1148 (Fed. Cir. 2012). [The] PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in applicant's specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). In this case, after describing the manufacture of the transistor, including forming the gate on the sides, top, and bottom of the body 25 (Spec. i-fi-134, 37), the Specification concludes that "a method has been described for forming a gate entirely around a silicon body in a replacement gate process." Id. at i139. In view of this description, it would be unreasonable to read "entirely around" to include the ends of the body 25 which would make the transistor inoperable. The rejection under § 101 is reversed. 3. REJECTION UNDER SECTION 103 The Examiner found that Kim describes a transistor structure that comprises the semiconductor body, source and drain regions, and gate stack of claim 1. Final Rej 'n 9--10. The Examiner made similar findings for claims 8, 15, and21. Id. at 10-12. 5 Appeal2013-000704 Application 13/042,973 The Examiner found that Kim does not "explicitly state" that the gate stack is "entirely around" the semiconductor body, but determined it would be obvious to do so "in order to have better control over the induction of current into the structure." Id. at 12. The Examiner also found that Kim does not describe "a portion of the gate stack is disposed in a cavity disposed in the insulator layer of the substrate" as required by the claim, but found that Fig. 15 of Dennard 1 teaches such a configuration. Id. The Examiner stated that it would have been obvious to dispose a portion of the gate stack in a cavity in the insulator layer of the substrate "to improve the device characteristics by using back gate functions." Id. at 13. Appellants state that Dennard discloses "an implanted back-gate formed into a Si-containing layer of an SOI wafer." Appeal Br. 13. Appellants contend that "the implanted back-gate is formed on a buried oxide layer of the SOI wafer, but not in a cavity disposed in the insulator layer of the substrate" as required by the claims. Id. The Examiner responded: Dennard et al. teach[ es] in figure 15 a portion of gate stack 24 is surrounded in all three sides by insulating layers 12 and 22. A cavity is defined by "Merriam Webster" Dictionary on line as 1 The Examiner mistakenly referred to Fig. 15 of Kim on page 12 of the Final Rejection, when Fig. 15 of Dennard was intended. In the Appeal Brief, Appellants noted that there was "no formal reference to Dennard ... used in the substance of the rejection," but Appellants addressed Dennard's disclosure and therefore appeared to understand the basis of the rejection. Appeal Br. 13. In the Answer, the Examiner corrected the error. Answer 18. Appellants filed a Reply Brief, repeating the same argument for Dennard as in the Appeal Brief. Reply Br. 2-3. Thus, we determine the error was harmless. 6 Appeal2013-000704 Application 13/042,973 '"an unfilled space within a mass". Clearly, unfilled space 24 within the mass of insulating layers 12, 22 is a cavity. Since insulating layers 12 and 22 are part of the substrate, then Dennard et al. teach a gate stack disposed in a cavity disposed in the insulator layer of the substrate, as claimed. Answer 18. The Examiner's finding is supported by a preponderance of the evidence. Fig. 15 of Dennard is reproduced below: F!G.15 Fig. 15 of Dennard shows a silicon-on-insulator (SOI) transistor. Dennard, Abstract; col. 2, 11. 53-57. Structure 12 (bottom right) is a buried oxide region (id. at col. 3, 11. 4--16); 22 and 34 are trench isolation regions (id. at col. 4, 11. 20-23; col. 6, 11. 54--55); 24 is a back-gate region formed into the Si-containing layer (id. at col. 5, 11. 7-8). Fig. 15, as found by the Examiner, shows the trench isolation regions 22 and 34 forming a defined space which surrounds the back-gate region 24. 7 Appeal2013-000704 Application 13/042,973 While Dennard does not characterize the space formed by the trench isolation regions as a cavity, the explicitly shown space (see 34, 23, 12, 22, 34 above) meets the definition cited by the Examiner. Answer 18. Appellants did not provide an adequate reason as to why this defined space is not a "cavity" as required by the claims. For the foregoing reasons and those of the Examiner, we affirm the obviousness rejection of claim I. Claims 3-8, 10-15, 17-19 and 21-23 were not argued separately and therefore fall with claim 1. 37 C.F.R. § 41.37(c)(iv). TIME PERIOD No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). AFFIRMED 8 Copy with citationCopy as parenthetical citation