Ex Parte Purwin

Patent Trial and Appeal Board

Oct 23, 2012

11037177 (P.T.A.B. Oct. 23, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/037,177 01/19/2005 Charles J. Purwin 1875.7060000 7294
26111 7590 10/23/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
CLEARY, THOMAS J
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
10/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte CHARLES J. PURWIN
____________________

Appeal 2010-010151
Application 11/037,177
Technology Center 2100
____________________

Before: ALLEN R. MacDONALD, MICHAEL J. STRAUSS, and
HUNG H. BUI, Administrative Patent Judges.

STRAUSS, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-010151
Application 11/037,177

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STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134 from a rejection of claims
1-3, 5-8, 10-19, 21, and 23-25. Claims 4, 9, 20 and 22 are canceled. We
have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Claims 1 and 19, reproduced below, are illustrative of the claimed
subject matter (emphasis added):
1. A circuit board assembly, comprising:
a circuit board;
a first bus interface connector mounted to the circuit
board, the first bus interface connector configured for a
Peripheral Component Interconnect-Extended (PCI-X) interface
protocol;
a second bus interface connector mounted to the circuit
board, the second bus interface configured for a Peripheral
Component Interconnect - Express (PCI-E) interface protocol;
an integrated circuit chip or chip set mounted to a first
surface of the circuit board and configured to interface with at
least one of the first and second bus interface connectors;
a first set of connector ports selectively coupled to the
chip or chip set when the first bus interface connector is
enabled;
and a second set of connector ports selectively coupled to
the chip or chip set when the second bus interface connector is
enabled;
wherein the first and second sets of connector ports are
mounted centrally onto a second surface of the circuit board,
opposite to the first surface; 1
wherein the circuit board is insertable into a motherboard
by selectively inserting either the first or the second bus
interface connector into a corresponding slot of the
motherboard.

1 See the embodiment illustrated at Figure 5 of the Specification.
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19. A method of fabricating a dual bus interface circuit board,
comprising:
mounting a chip or chipset on the circuit board;
mounting a first bus interface connector and a second bus
interface connector to the circuit board, wherein the first bus
interface connector comprises a Peripheral Component
Interconnect-Extended (PCI-X) connector and the second bus
interface connector comprises a Peripheral Component
Interconnect-Express (PCI-E) connector;
routing a first set and a second set of signal traces from
the chip or chipset to the first and second bus interface
connectors, respectively;
selectively mounting resistors at first ends of one or more
of the first and the second sets of signal traces to selectively
enable one or more of the first and second bus interface
connectors;
coupling a first set of connector ports to the chip or
chipset when the first bus interface connector is enabled; and
coupling a second set of connector ports to the chip or
chipset when the second bus interface connector is enabled;
wherein the circuit board is insertable into a motherboard
by selectively inserting either the first or the second bus
interface connector into a corresponding slot of the
motherboard.

REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Sharp EP 0350573 Jan. 17, 1990
Pretchel
Howell
US 4,795,602
US 6,142,357
Jan. 3, 1989
Nov. 7, 2000
Chen
Lavie
US 2004/0143694 A1
US 2005/0042931 A1
Jul. 22, 2004
Feb. 24, 2005
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Application 11/037,177

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The Free On-Line Dictionary of Computing, Online 25-June 1997.
Retrieved from Internet 20-September 2006.
(“FOLDOC”).
“Adaptor Card For Personal Computer”, IBM Technical Disclosure
Bulletin, IBM Corp., October 1, 1988, Vol. 31, No.5, IBM Corp, New York,
NY (“IBM”).
The American Heritage College Dictionary, Fourth Edition. 2002.
Houghton Mifflin Company, page 234, ISBN 0-618-19848-8.
The Microsoft Press Computer Dictionary, Second Edition, 1994,
Microsoft Press, page 309. ISBN 1-55615-597-2.

REJECTIONS2
The Examiner made the following rejections:
Claims 1-3, 5-6, 8,13, and 16-18 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Sharp, Appellant’s admitted prior art
(“AAPA”) and Howell. Ans. 4.
Claims 7, 10, and 12 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sharp, AAPA, Howell and Chen. Ans. 9.

2 In connection with the rejection under 35 U.S.C. § 103(a) over the
combination of Sharp, AAPA and Howell, Appellant collectively argues
claims 1-3, 5-6, 8, 13, and 16-18 based on claim 1 (App. Br. 8-10) while
independent claim 19 and dependent claims 7, 10, 12, 14, 15, 21, and 23-25
are not argued separately (App. Br. 10-14). In connection with the rejection
under 35 U.S.C. § 103(a) over the combination of IBM, AAPA and Howell,
Appellant collectively argues claims 1-3, 5-6, 8, 11, 13, and 16-18 based on
claim 1 (App. Br. 14-16) while independent claim 19 and dependent claims
15 are not argued separately (App. Br. 10-14). In view of the foregoing, we
select claim 1 as representative of all pending claims.
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Application 11/037,177

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Claim 14 stands rejected under 35 U.S.C. 103(a) as being
unpatentable over Sharp, AAPA, Howell and FOLDOC. Ans. 11.
Claim 15 stands rejected under 35 U.S.C. 103(a) as being
unpatentable over Sharp, AAPA, Howell and Lavie. Ans. 11.
Claims 19 and 25 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sharp, AAPA and Pretchel. Ans. 12.
Claims 21 and 23 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sharp, AAPA, Pretchel and Chen
Claim 24 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sharp, AAPA, Pretchel and Howell. Ans. 16.
Claims 1-3, 5-6, 8, 11, 13, and 16-18 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over IBM, AAPA and Howell. Ans. 17.
Claim 15 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over IBM, AAPA, Howell and Lavie. Ans. 22.
Claim 19 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over IBM, AAPA and Pretchel. Ans. 22.

Appellant’s Contentions
1. Appellant contends that the Examiner erred in rejecting claims
1-3, 5-6, 8, 13, and 16-18 over the combination of Sharp, AAPA and Howell
because:
(i) “Sharp discloses a single pin and socket header or connector 34,
and thus does not teach or suggest ‘a first set of connector ports’ and a
‘second set of connector ports,’ as recited in claim 1.” App. Br. 8 (emphasis
omitted).
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(ii) “Sharp does not teach or suggest that connector 34 is coupled to
the chip or chip set, nor that connector 34 is in any way related to the
supported bus interface protocols or to which bus interface protocol is
enabled.” App. Br. 9 (emphasis omitted).
2. Appellant contends that the Examiner erred in rejecting claims
1-3, 5-6, 8, 11, 13, and 16-18 over the combination of IBM, AAPA and
Howell because interface circuits 4 and 5 of IBM are not equivalent to the
claimed first and second set of connector ports. App. Br. 15; Reply 5.

Issues on Appeal
Based on Appellant’s arguments in the Appeal Brief (App. Br. 8-17)
and the Reply Brief (Reply Br. 2-6), the issues presented on appeal are:
1. Did the Examiner err in concluding that the combination of
Sharp, AAPA and Howell teaches or suggests first and second sets of
connector ports selectively coupled to the chip or chip set when the
respective bus interface connector is enabled?
2. Did the Examiner err in concluding that the combination of
IBM, AAPA and Howell teaches or suggests first and second sets of
connector ports selectively coupled to the chip or chip set when the
respective bus interface connector is enabled?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments (Appeal Brief and Reply Brief) that the Examiner has erred. We
concur with Appellant’s conclusions that the Examiner erred in finding that
either the combination of Sharp, AAPA and Howell or the combination of
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IBM, AAPA and Howell teaches or suggests “a first set of connector ports
selectively coupled to the chip or chip set when the first bus interface
connector is enabled” and “a second set of connector ports selectively
coupled to the chip or chip set when the second bus interface connector is
enabled.”

Contention 1
Addressing contention 1, apparatus claim 1 requires “a first set of
connector ports selectively coupled to the chip or chip set when the first bus
interface connector is enabled” and “a second set of connector ports
selectively coupled to the chip or chip set when the second bus interface
connector is enabled.” Independent method claim 19 contains similar
limitations.
The Examiner sets forth grounds of rejection for the disputed
limitations, as follows:
Sharp … discloses that circuit boards often have connections
(first and second sets of connector ports) to multiple external or
non motherboard devices (See Figures 1 and 2 Number 34,
Column 2 Lines 41-46, and Column 5 Lines 31-36).

Ans. 5.
Appellant presents the following principal argument:
Sharp discloses a single pin and socket header or connector 34,
and thus does not teach or suggest “a first set of connector
ports” and a “second set of connector ports,” as recited in claim
1. In the Response to Applicant's Arguments, the Examiner now
contends that “the single pin and socket connector 34 is
comprised of multiple individual pin and socket connectors,
wherein each pin and socket is a connector port in accordance
with the broadest reasonable interpretation of the term.” See,
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Office Action, page 23. However, this interpretation is
untenable. The term “connector port” has a well known
meaning in the art to which this invention pertains, and it would
be inconsistent with that meaning to hold that a single in/socket
in a pin and socket header is by itself a connector port.

App. Br. 8-9.
We agree with Appellant that the Examiner erred in finding that the
single connector 34 of Sharp is equivalent to the claimed first and second
connector ports. While the Examiner cites to The Microsoft Press Computer
Dictionary, Second Edition, for support of a broad interpretation of the term
“port”, the interpretation must be consistent with the specification. See
Phillips v. AWH Corp., 415 F.3d 1303, 1313-14 (Fed. Cir. 2005). Here the
Examiner’s interpretation of entire phrase “connector ports” is not consistent
with Appellant’s specification. Instead, Appellant’s specification discloses
connector ports to be distinct hardware used to attach matching cables. See,
e.g., Spec. 9. Furthermore, Appellant’s claim 1 recites first and second sets
of connector ports which are selectively coupled to a chip or chip set. In
contrast, Sharp discloses a single unified connector 34 (albeit with multiple
pins) “for cooperation with a ribbon cable and plug for connection to
external devices.” Sharp, col. 5, ll. 31-36 (emphasis ours). We further note
that a more recent 2002 edition of the cited Microsoft Computer Dictionary
(i.e., having a publication date three rather than eight years prior to the filing
date) describes that “[p]orts typically accept a particular type of plug used
for a specific purpose.”3 This later description further supports Appellant’s
argument that “a person skilled in the art would understand that the ‘first set

3 The Microsoft Press Computer Dictionary, Fifth Edition. 2002,
Microsoft Press. Page 412. ISBN 0-7356-1495-4
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Application 11/037,177

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of connector ports’ are separate and distinct from the ‘second set of
connector ports.’” App. Br. 9. We therefore conclude that the single
connector of Sharp is not equivalent to the claimed first and second
connector ports.
Accordingly, we will not sustain the Examiner’s rejection of claim 1
under 35 U.S.C. § 103(a) as being unpatentable over Sharp, AAPA and
Howell and its dependent claims 2, 3, 5, 6, 8, 13 and 16-18. Neither do we
sustain the rejection of independent claim 19 and its dependent claim 25
over Sharp, AAPA and Pretchel for the reasons presented in connection with
claim 1, noting that Pretchel also fails to cure the deficiency noted with
respect to claim 1. Further we do not sustain the rejections of claims 7, 10,
and 12 over Sharp, AAPA, Howell and Chen, claim 14 over Sharp, AAPA,
Howell and FOLDOC, claim 15 over Sharp, AAPA, Howell and Lavie,
claims 21 and 23 over Sharp, AAPA, Pretchel and Chen or claim 24 over
Sharp, AAPA, Pretchel and Howell, the additional references again failing to
cure the deficiency noted above with respect to parent claim 1.

Contention 2
In connection with contention 2, Appellant argues that interface
circuits 4 and 5 of IBM are not equivalent to the claimed first and second set
of connector ports. App. Br. 9. The Examiner responds that “[e]lements
4 and 5 are ‘Interface Circuits’, and thus are interface ports in accordance
with the broadest reasonable interpretation of the term.” Ans. 27. We
disagree. Interface circuit 4 and 5 are not connectors and, therefore, would
not be understood by one skilled in the art to constitute or be equivalent to
the claimed connector ports.
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Application 11/037,177

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Accordingly, we will not sustain the Examiner’s rejection of claim 1
under 35 U.S.C. § 103(a) as being unpatentable over IBM, AAPA and
Howell or of dependent claims 2, 3, 5, 6, 8, 11, 13 and 16-18. Neither do we
sustain the rejection of independent claim 19 over IBM, AAPA and Pretchel
for the reasons presented in connection with claim 1, noting that Pretchel
also fails to cure the deficiency noted above with respect to claim 1. Nor do
we sustain the rejections of claim 15 over IBM, AAPA, Howell and Lavie,
noting that Lavie further fails to cure the deficiency with respect to parent
claim 1.

CONCLUSIONS
The Examiner has erred both in rejecting claims 1-3, 5-8, 10, 12-19,
21 and 23-25 as unpatentable under 35 U.S.C. § 103(a) as being obvious
over the combination of Sharp, AAPA, Howell, Chen, FOLDOC, Lavie
and/or Pretchel, and in rejecting claims 1-3, 5, 6, 8, 11, 13 and 15-19 under
35 U.S.C. § 103(a) as being obvious over the combination of IBM, AAPA,
Howell, Lavie and/or Pretchel.

DECISION
The rejections of claims 1-3, 5-8, 10-19, 21 and 23-25 are reversed.

REVERSED

msc