Ex Parte Preisach

Board of Patent Appeals and Interferences

Oct 25, 2011

10752597 (B.P.A.I. Oct. 25, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
________________

Ex parte HELMUT PREISACH
________________

Appeal 2009-008583
Application 10/752,597
Technology Center 2800
________________

Before MAHSHID D. SAADAT, MARC S. HOFF, and
THOMAS S. HAHN, Administrative Patent Judges.

HAHN, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING
Appeal 2009-008583
Application 10/752,597

2
Appellant, in a Request for Rehearing, filed October 3, 2011,
(hereinafter “Request” or “Req. for Reh’g”), asks for our reconsideration of
the Panel’s Decision of August 1, 2011 (hereinafter “Decision”), wherein we
affirmed-in-part the rejections made by the Examiner. Specifically,
Appellant submits that we “misunderstood at least one critical aspect of the
invention defined in independent claims 1 and 9” (Req. for Reh’g 1).

OPINION
As addressed infra, the Decision has been reconsidered in view of the
Request and no errors have been found. Therefore, the Decision is
unchanged for the following reasons.
In the Request, Appellant points out that both of claims 1 and 9 cover
an integrated electrical switching matrix chip having multiple inputs and
outputs with a matrix of crosspoint switches (Req. for Reh’g 1). Appellant
particularly relies on each of these claims reciting that “said inputs and said
outputs are arranged on said chip in the shape of a cross dividing said matrix
into four sectors” (id.).
Claims 1 and 9, with the other appealed claims, stand rejected under
35 U.S.C. § 102(b) as being anticipated by Kusunoki (Final Action 2-3).
The Examiner finds Kusunoki teaches in Figure 9 that:
[I]nputs and outputs (wires Ls, Ls, Us and Rs) are arranged
coming into the SMX [cross point switch matrix (see col. 1, ll.
33-35)] from four different directions, perpendicular to each
other. That is considered to be a shape of a cross. Furthermore,
the SMX can be divided into four sections as a matter of choice.
The [E]xaminer defined the four sectors as being each one-
fourth section of the SMX.
Appeal 2009-008583
Application 10/752,597

3
(Ans. 5). Appellant quotes these identified findings and argues that “the
wires Ls, LS, Us and Rs are not the inputs and outputs of the chip. They are
connection wires, even as characterized by the [E]xaminer” (Req. for Reh’g
2). Continuing with this argument, Appellant contends that “[e]ven if these
lines divide the SMX into four quadrants, this still does not constitute the
chip inputs and outputs arranged in the shape of a cross” (id.).
Without citation to evidence or submission of corroborating argument,
Appellant next asserts that the “Ls, Ls, Us and Rs [wires] are not in the
shape of a cross dividing the switch matrix into four quadrants” (Req. for
Reh’g 3). Based on our review of Kusunoki, including Figure 9, we agree
with the Examiner and find the identified wires are in the shape of a cross
dividing a switch matrix into four quadrants. We disagree with Appellant’s
conclusory assertion.
As a final argument, Appellant contends that “importantly, the wires
are not the chip inputs and outputs” (id.). Appellant points out that the
Kusunoki “Input/Output Cells (IOC) are shown in Fig. 1(A), and described
at lines 18-25 of col. 4, as being arranged around the periphery of the chip as
is conventional” (id.). We agree that Kusunoki teaches positioning
input/output (I/O) buffer cells (IOC) along chip peripheries to surround
circuits (col. 4, ll. 18-20). However, we disagree with Appellant’s argument
that this disclosure is “in direct contradiction to the claim requirement of
having the inputs and outputs arranged in the form of a cross that divides the
matrix into quadrants” (Req. for Reh’g 3). We do not find contradiction
with the claim because, although Kusunoki teaches positioning input/output
buffer cells along chip peripheries, the respective input and output signals
have to be communicated to included circuits. The Examiner recognized
Appeal 2009-008583
Application 10/752,597

4
this requirement and indicated that Appellant’s “argument is not persuasive
in that Lines L1 and L2 [are] considered to be input[] lines [i.e., conductors
or wires] because they provide a medium for input signals to circuitry” (Ans.
7). Both claims 1 and 9 recite “inputs” and “outputs” without narrowing
limitations for these elements aside from these elements being arranged in a
cross. Consequently, we agree with the Examiner that the identified
Kusunoki lines provide inputs and outputs, i.e., signals, and, as shown in
Figure 9, the lines are arranged in a cross.

DECISION
The Request has been granted to the extent of reconsidering the
Decision, but the Request is denied with respect to making any
modifications of the Decision.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

REHEARING DENIED

babc