Ex Parte Poelzl

Patent Trial and Appeal Board

Jan 30, 2017

13652758 (P.T.A.B. Jan. 30, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/652,758 10/16/2012 Martin Poelzl 1012-0463 1843
57579 7590 02/01/2017
MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES
1255 Crescent Green
Suite 200
CARY, NC 27518
EXAMINER
ENAD, CHRISTINE A
ART UNIT PAPER NUMBER
2823
NOTIFICATION DATE DELIVERY MODE
02/01/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte INFINEON TECHNOLOGIES AUSTRIA AG
Appeal 2016-000502
Application 13/652,758
Technology Center 2800
Before BEVERLY A. FRANKLIN, LINDA M. GAUDETTE, and
DONNA M. PRAISS, Administrative Patent Judges.
GAUDETTE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2016-000502
Application 13/652,758
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s decision2
finally rejecting claims 1—5, 7, 22, and 23. Br. 2. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.
The invention relates to “manufacturing methods for semiconductor devices,
in particular trench gate field effect semiconductor devices with reduced Miller
capacitance.” Specification filed Oct. 16, 2012 (“Spec.”) 12. “Miller capacitance
... is related to the gate-drain charge Qgd between the gate electrode and the drain
region of the field effect transistor.” Id. 14. Reducing Miller capacitance, e.g., by
reducing Qgd, improves transistor switching speed and/or reduces losses. Id.
Claim 1, the sole independent claim on appeal, is reproduced below:
1. A method for forming a semiconductor device, comprising:
providing a semiconductor body having a horizontal surface;
forming an epitaxy hard mask on the horizontal surface;
forming an epitaxial region by selective epitaxy on the
horizontal surface relative to the epitaxy hard mask so that the
epitaxial region is adjusted to the epitaxy hard mask;
polishing the epitaxial region by a chemical-mechanical
polishing process stopping on the epitaxy hard mask;
forming a vertical trench from the horizontal surface into the
semiconductor body;
forming an insulated field plate in a lower portion of the
vertical trench comprising
forming a field oxide; and
1 Appellant identifies the real party in interest as Infineon Technologies Austria
AG. Appeal Brief filed Feb. 20, 2016 (“Br.”), 2.
2 Final Office Action mailed Aug. 14, 2014 (“Final Act.).
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Appeal 2016-000502
Application 13/652,758
forming an insulated gate electrode above the insulated field
plate such that the field oxide extends, in a vertical direction, up to the
epitaxial region.
Br. 9 (Claims App’x).
The claims stand rejected as unpatentable under pre-AIA 35 U.S.C. § 103(a)
as follows:
1. claims 1, 3—5, 7, and 23 over Challa et al. (US 2005/0167742 Al,
issued Aug. 4, 2005 (“Challa”)) in view of de Fresart et al. (US 2008/0050877 Al,
published Feb. 28, 2008 (“de Fresart”));
2. claim 2 over Challa, de Fresart, and Disney (US 2009/0233407 Al,
published Sept. 17, 2009); and
3. claim 22 over Challa, de Fresart, and Quddus (US 2010/0059849 Al,
published Mar. 11, 2010).
The Examiner finds Challa discloses a method for forming a semiconductor
device that differs from the method of appealed claim 1 in that Challa does not
form an epitaxy hard mask. Final Act. 2—3. Thus, although Challa discloses
forming an epitaxial region by selective epitaxy, this step is not conducted relative
to an epitaxy hard mask as required by claim 1. See id. at 3. Likewise, Challa’s
method does not include a step of “polishing the epitaxial region by a chemical-
mechanical polishing process stopping on the epitaxy hard mask” (claim 1
(emphasis added)). See Final Act. 3. The Examiner finds de Fresart discloses a
method for forming a semiconductor device that includes a step of “forming an
epitaxy hard mask on [a] horizontal surface” of the semiconductor body as recited
in claim 1, as well as subsequent steps of forming and polishing an epitaxial region
in the manner recited in claim 1. Id. at 3^4.
Appellant does not dispute the aforementioned findings by the Examiner.
See generally Br. 4—8.
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Appeal 2016-000502
Application 13/652,758
The Examiner finds one of ordinary skill in the art would have
substituted/modified Challa’s method of forming an epitaxial layer with de
Fresarf s method of forming an epitaxial layer using an epitaxy hard mask because
de Fresart’s method is merely a known alternative to Challa’s method of growing
patterned epitaxial regions on a semiconductor substrate. See Final Act. 10;
Examiner’s Answer mailed July 28, 2015 (“Ans.”), 4.
Appellant does not dispute that Challa, as modified by de Fresart, would
result in a method as recited in claim 1. See generally Br. 4—7. Appellant argues,
however, that the Examiner fails to identify persuasive evidence to support a
finding that one of ordinary skill in the art would have modified Challa’s method
to include de Fresarf s technique of forming an epitaxy hard mask prior to forming
an epitaxial region. See id. Appellant argues, for example, that there is no
evidence to support the Examiner’s finding that “the teachings of the de Fresart
reference are any more efficient tha[n] what is disclosed in the Challa reference.”
Id. at 7 (emphasis omitted).
A prima facie case of obviousness is established where the Examiner
demonstrates that the invention is nothing more than the predictable result of a
combination of familiar elements according to known methods. KSR Int'l. Co. v.
Teleflex Inc., 550 U.S. 398, 416 (2007).
In rejecting the claims, the Examiner relies on Challa’s description of an
embodiment shown in Figures 38A—D. See Final Act. 2—3. Challa discloses that
Figures 3 8A—D show “a simplified process flow for one example of a self-aligned
epi-well trench device with buried electrode (or shielded gate).” Challa 1168
(emphasis added). Challa clearly states, however, that the invention is not limited
to the process disclosed in Figures 3 8A—D. See id. 1170 (“Other methods of
forming SEG mesa structures are described in commonly-assigned U.S. Pat. No.
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Appeal 2016-000502
Application 13/652,758
6,391,699 . . . and U.S. Pat. No. 6,373,098,. . . incorporated by reference in their
entirety.”). This disclosure supports the Examiner’s finding that Challa teaches the
method as described in connection with Figure 38 may be modified to use any
suitable, known technique for forming a patterned epitaxial region. Appellant has
not shown error in the Examiner’s finding that one of ordinary skill in the art
would have understood that de Fresart discloses an equivalent, known technique
for forming a patterned epitaxial region, and, therefore, would have had a
reasonable expectation of success in replacing Challa’s technique with de Fresart’s
technique. An “[ejxpress suggestion to substitute one equivalent for another need
not be present to render such substitution obvious.” In re Font, 675 F.2d 297, 301
(CCPA 1982); see also In reMayne, 104 F.3d 1339, 1340 (Fed. Cir. 1997) (noting
that the substitution of one known element for a known equivalent is prima facie
obvious).
Accordingly, we are not convinced of error in the Examiner’s conclusion of
obviousness as to claim 1. Appellant does not present separate arguments in
support of patentability of dependent claims 3—5, 7, 22, and 23. See generally Br.
4—8. Therefore, we sustain the Examiner’s Section 103(a) rejections of claims 1,
3—5, 7, 22, and 23.
We have considered Appellant’s additional argument in support of
patentability of dependent claim 2 (Br. 7—8), but are not persuaded of error in the
Examiner’s conclusion of obviousness as to claim 2 for the reasons explained by
the Examiner in the Answer (Ans. 4—5). Accordingly, we likewise sustain the
Examiner’s Section 103(a) rejection of claim 2 for the reasons expressed in the
Final Office Action (Final Act. 6—7) and the Answer (Ans. 4—5).
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. §1.136(a)(l)(iv).
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Appeal 2016-000502
Application 13/652,758
AFFIRMED
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