Ex Parte Plondke et alDownload PDFPatent Trial and Appeal BoardNov 30, 201813398927 (P.T.A.B. Nov. 30, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/398,927 02/17/2012 Erich James Plondke 12371 7590 12/04/2018 Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM 4000 Legato Road, Suite 310 Fairfax, VA 22033 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. QC111779 9795 EXAMINER BIRKHIMER, CHRISTOPHER D ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 12/04/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): meo.docket@mg-ip.com meo@mg-ip.com ocpat_uspto@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ERICH JAMES PLONDKE, AJAY AN ANT INGLE, and LUCIAN CODRESCU1 Appeal2017-002269 Application 13/398,927 Technology Center 2100 Before ROBERT E. NAPPI, JOHNNY A. KUMAR, and JUSTIN BUSCH, Administrative Patent Judges. NAPPI, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) from the final rejection of claims 1, 2, 4, 8, 11 through 14, 18 through 21, and 23. We have jurisdiction under 35 U.S.C. § 6(b ). We affirm-in-part. 1 According to Appellants, the real party in interest is QUALCOMM Incorporated. App. Br. 3. Appeal2017-002269 Application 13/398,927 INVENTION The invention is directed to a technique for performing non-allocating memory access instructions using physical addresses and bypassing virtual- to-physical address translation, thereby avoiding allocating intermediate levels of cache. Abstract; Spec. ,r 2. Claim 1 is illustrative of the invention and is reproduced below. 1. A method for accessing memory comprising: specifying a physical address in a load instruction initiated by a processor, the physical address corresponding to a physical location in at least one or more caches or the memory, wherein the load instruction designates use of the one or more caches, and wherein the one or more caches are configured between the processor and the memory; and executing the load instruction, comprising: avoiding virtual-to-physical address translation; querying the one or more caches for data associated with the physical address; and if a miss is encountered in one or more of the caches for the physical address, avoiding allocation of the one or more caches in which a miss was encountered. REJECTION AT ISSUE2 The Examiner has rejected claims 1, 2, 4, 8, 11 through 14, 18 through 21, and 23 under 35 U.S.C. § 103 (a) as being unpatentable over Moyer (US 7,376,807 B2, issued May 20, 2008) and Momose (US 2009/0100232 Al, published Apr. 16, 2009). Final Act. 5-16. 2 Throughout this Decision, we refer to the Appeal Brief ("App. Br.") filed June 21, 2016, the Reply Brief ("Reply Br.") filed December 2, 2016, Final Office Action ("Final Act.") mailed March 1, 2016, and the Examiner's Answer ("Ans.") mailed October 5, 2016. 2 Appeal2017-002269 Application 13/398,927 ANALYSIS We have reviewed Appellants' arguments in the Briefs, the Examiner's rejection, and the Examiner's response to Appellants' arguments. Appellants' arguments have persuaded us of error in the Examiner's obviousness rejection of claims 11 through 14, 18 through 21, and 23. Appellants argue the Examiner's rejection of independent claims 1, 11, 20, and 23 is in error. App. Br. 6-9; Reply Br. 2--4. The issue presented by these arguments is, did the Examiner err in finding that Momose teaches if a cache miss is encountered, avoiding allocation of one or more caches in which the miss was encountered as recited in each of the independent claims? In response to Appellants' arguments, the Examiner finds that Momose teaches an operation mode causes instructions to be provided with cache use, as claimed. Answer 2 ( citing Momose para. 45). The Examiner finds that when a cache miss results in steps S 108-S 110 being executed, the cache allocation is avoided with a NO determination at step S 109. Answer 2-3 ( citing Figure 6). The Examiner finds that Momose teaches that the operation mode can be changed dynamically during processor operation which includes during the execution of a load instruction and thus the cache use can be changed any time after step S 107. Answer 2-3 ( citing Momose paras. 46--47). Based upon these findings the Examiner states "this would result in no allocation in the cache after a cache miss even though the instruction indicates a cache usage since the operation mode indicates no cache use and the operation mode is preferentially used over the instruction mode." Answer 3. 3 Appeal2017-002269 Application 13/398,927 At the outset, we are not persuaded of error in the Examiner's rejection of claim 1 by Appellants' arguments as they are not commensurate with the broadest reasonable interpretation of method claim 1. The limitation to which Appellants' arguments are directed, an instruction initiated by a processor where executing the load instruction includes, if a miss is encountered, avoiding allocation of one or more caches, is a conditional step. As such, in considering the broadest reasonable interpretation of method claim 1, the steps dependent upon the condition would not necessarily be invoked and as such it is not incumbent upon the Examiner to show that the art performs those steps. See Ex parte Ex parte Schulhauser, No. 2013-007847, 2016 WL 6277792, at *3--4 (PTAB Apr. 28, 2016) (precedential) (holding that in a method claim, a step reciting a condition precedent does not need to be performed if the condition precedent is not met). See also MANUAL OF PATENT EXAMINING PROCEDURE (MPEP) § 2111.04(II) (9th ed. Rev. 08.2017, Jan. 2018) ( citing Schulhauser) and In re Johnston, 435 F.3d 1381, 1384 (Fed. Cir. 2006) ("[O]ptional elements do not narrow the claim because they can always be omitted.").Gary M. Katz, Appeal No. 2010-006083, 2011 WL 1211248, at *2 (BP AI Mar. 25, 2011) ( citing In re Am. A cad. of Sci. Tech. Ctr., 3 67 F .3d 1359, 1364 (Fed. Cir. 2004)). The limitations at issue in Appellants' arguments, discussed above, are recited as being responsive to a cache miss, and as such Appellants' arguments are not commensurate with the broadest reasonable interpretation of method claim 1, where a cache miss does not occur. Accordingly, we are not persuaded of error in the Examiner's rejection of independent claim 1 and dependent claims 2, 4, and 8 and we sustain the rejection of these claims. 4 Appeal2017-002269 Application 13/398,927 However, we reach a different conclusion with respect to system claims 11, 20, and computer readable medium claim 23, which stand similarly rejected. Our decisions have drawn a distinction between method claims and system/apparatus claims for purposes of conditional "if' language. See Schulhauser, 2016 WL 6277792, at *7 ( determining that the "broadest reasonable interpretation of a system claim having structure that performs a function, which only needs to occur if a condition precedent is met, still requires structure for performing the function should the condition occur"); Each of independent claims 11, 20, 23, and the claims which depend upon them recite a limitation directed to an instruction initiated by a processor where executing the load instruction includes, if a miss is encountered, avoiding allocation of one or more caches. We disagree with the Examiner's rationale, discussed above, which relies upon the finding that the operation mode changes after step S 107 in Figure 6, to show the limitation directed to issuing an instruction to avoid cache usage if there is a miss. We have reviewed paragraphs 46 and 4 7 cited by the Examiner as teaching this feature and we agree the operation mode is dynamic during the operation of the program being executed by the processor; we do not, however, find that the cited paragraphs identify a mode change in the middle of implementing the process of issuing the load instruction shown in Figure 6. Rather, paragraph 45 makes clear that the flow cart, which includes checking the status of the mode ( step S 101) occurs at the time of issuing the load instruction. Accordingly, we do not sustain the Examiner's rejection of independent claims 11, 20, and 23, and dependent claims 12 through 14, 18, 19, and 21. 5 Appeal2017-002269 Application 13/398,927 DECISION The decision of the Examiner to reject claims 1, 2, 4, and 8 under 35 U.S.C. § 103 is affirmed. The decision of the Examiner to reject claims 11 through 14, 18 through 21, and 23 under 35 U.S.C. § 103 is reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED-IN-PART 6 Copy with citationCopy as parenthetical citation