Ex Parte Piwonka et al

Patent Trial and Appeal Board

Jan 27, 2017

13120652 (P.T.A.B. Jan. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/120,652 03/23/2011 Mark A Piwonka 82681281 2075
22879
HP Tnr
7590 01/31/2017 EXAMINER
3390 E. Harmony Road
Mail Stop 35
DANG, KHANH
FORT COLLINS, CO 80528-9544 ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
01/31/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipa.mail@hp.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MARK PIWONKA, LOUIS B. HOBSON, and
ROBERT C. BROOKS
Appeal 2015-0071551
Application 13/120,652
Technology Center 2100
Before JEAN R. HOMERE, JOHN A. EVANS, and
DANIEL J. GALLIGAN, Administrative Patent Judges.
Per Curiam.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1—19. App. Br. 5. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellants ’ Invention
Appellants’ invention is directed to a voltage converter to manage
power in a system having a processor. Spec. 5—6, Fig. 1. In particular,
1 Appellants identify the real party in interest as Hewlett-Packard
Development Company, LP. App. Br. 1.
Appeal 2015-007155
Application 13/120,652
the processor (100) provides indications to a controller (104) to adjust
voltage provided to the processor from a power supply (102), such as to
provide higher voltage for a “higher” performance state at higher power
consumption or a lower voltage for a “lower” performance (sleep) state at
lower power consumption. Id.
Independent claim 1 is illustrative, and reads as follows:
1. An apparatus to manage power in a system having
a processor, comprising:
a voltage converter to provide a power voltage to the
processor, wherein the processor is able to transition among
different power modes, wherein the voltage converter is to
receive, from the processor, indications to specify different non­
zero voltage levels of the power voltage for at least two of the
power modes; and
a controller to:
detect, based on the indications, a transition of the
processor to a lower one of the power modes, and
in response to detecting transition of the processor
to the lower one of the power modes, disable at least one
portion of the voltage converter.
Illustrative Claim
Allen et al.
Park
Prior Art Relied Upon
US 7,203,847 B2 Apr. 10, 2007
US 7,334,141 B2 Feb. 19,2008
(“Allen”)
Crowther et al. US 2008/0197823 Al Aug. 21, 2008
(“Crowther”)
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Appeal 2015-007155
Application 13/120,652
Rejections on Appeal2
Claims 1—9, 11, 15, 16, and 19 stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Crowther. Final Act. 3—7.
Claims 10, 12—14, 17, and 18 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Crowther and Allen. Final Act. 7—13.
Claims 1—9, 11, 15, 16, and 19 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Park and Crowther. Final Act. 13—14.
Claims 10, 12—14, 17, and 18 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Park, Crowther, and Allen. Final Act. 14—19.
ANALYSIS
We consider Appellants’ arguments seriatim, as they are presented in
the Appeal Brief, pages 6—15, and the Reply Brief, pages 2—9.3
2 The Examiner has withdrawn the rejection of claims 1—12 and 17 under
35 U.S.C. § 112, first paragraph. Ans. 2.
3 Rather than reiterate the arguments of Appellants and the Examiner, we
refer to the Appeal Brief (filed February 4, 2015) (“App. Br.”), the Reply
Brief (filed July 27, 2015) (“Reply Br.”), and the Answer (mailed May 26,
2015) (“Ans.”) for the respective details. We have considered in this
Decision only those arguments Appellants actually raised in the Briefs. Any
other arguments Appellants could have made but chose not to make in the
Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv) (2012).
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Appeal 2015-007155
Application 13/120,652
Crowther
Appellants argue the power state indication (PSI) signal of Crowther
does not describe indications to specify different non-zero voltage levels of
the power voltage for at least two of the power modes, as recited in claim 1.
App. Br. 6—8; Reply Br. 2—6. In particular, Appellants assert that the PSI
signal of Crowther does not specify different non-zero voltage levels of
power voltage. App. Br. 7. Rather, according to Appellants, the PSI signal
indicates different loads corresponding to different current draws at a
stabilized voltage. App. Br. 8 (citing Crowther 19); Reply Br. 2, 3.
Appellants assert Crowther attempts to provide stable voltage. Reply Br. 3
(citing Crowther 177). Appellants contend phases shed or added in
Crowther do not result in the voltage level varying. Reply Br. 4 (citing
Crowther^ 13).
The Examiner responds that the PSI signal of Crowther causes an
adjustment in the power supplied to the processor. Ans. 7—11. The
Examiner finds the PSI signal instructs the converter to perform phase
shedding or phase adding depending on the power state of the processor.
Ans. 7 (citing Crowther || 4, 13, 18, 32, 46, and 63—66). The Examiner
finds Crowther describes the processor runs in either an idle state at low
power or a running state at high power. Ans. 8 (citing Crowther | 6). The
Examiner explains that the load on the processor is directly proportional to
the power drawn by the processor. Ans. 8. The Examiner additionally
explains that the power is the product of the voltage on the processor and the
current drawn by the processor. Id. The Examiner finds experimental
results from Crowther indicating different output voltage levels. Ans. 10—11
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Appeal 2015-007155
Application 13/120,652
(citing Crowther Figs. 8C, 8D). Figures 8C and 8D in Crowther depict the
PSI signal changing from one value to another value with corresponding
phase shedding/adding causing the output voltage to change from one non­
zero value to another non-zero value. See Crowther, Figs. 8C, 8D, 178.
At the outset, we note Appellants do not dispute the Examiner’s
finding regarding this variation in voltage. Reply Br. 5. Further, we agree
with the Examiner that Crowther describes the PSI signal indicates two non­
zero voltage values. Ans. 10—11 (citing Crowther Figs. 8C, 8D). Crowther
discloses that the output voltage stabilizes as quickly as possible to the new
voltage setting. See Crowther, Figs. 8C, 8D, 178. This is consistent with
the goal in Crowther, noted by Appellants, of providing a stable output
voltage. Reply Br. 3 (citing Crowther | 77). Accordingly, we are not
persuaded of error in the Examiner’s anticipation rejection of claim 1.
Regarding claim 15, Appellants argue the PSI in Crowther does not
specify transition of voltage levels of the power voltage to the processor.
App. Br. 9-10. Appellants also contend Crowther does not describe
detection of the processor entering a sleep state from a performance state.
Id. As discussed above, the Examiner finds Crowther discloses the PSI
signal causes the output voltage to change from one level to another level.
Ans. 10—11 (citing Crowther Figs. 8C, 8D). The Examiner explains the
processor in Crowther runs in either an idle state or a running state. Ans. 8
(citing Crowther | 6). Crowther describes detection of the processor
entering an idle operation state from a running state. See Crowther | 6.
Accordingly, we are not persuaded of error in the Examiner’s anticipation
rejection of claim 15.
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Appeal 2015-007155
Application 13/120,652
Crowther and Allen
Regarding claim 13, Appellants contend the PSI of Crowther does not
indicate the voltage level of the processor is being lowered to a first level.
App. Br. 11; Reply Br. 6—7. Appellants assert different loads in Crowther
correspond to different currents, not voltages. Id. The Examiner finds one
PSI indication specifies the low power state and another PSI indication
specifies the high power state. Ans. 14. As discussed above with respect to
claim 15, Crowther describes detection of the processor entering an idle
operation state from a running state. See Crowther 16. This corresponds to
a load step down to a lower voltage level. See Crowther 178, Fig. 8D.
Accordingly, we are not persuaded of error in the Examiner’s rejection of
claim 13 based on the combination of Crowther and Allen.
Park and Crowther
Appellants argue that the DEEPSLEEP and DEEPERSLEEP signals
in Park do not specify the recited different non-zero voltage levels, recited in
claim 1. App. Br. 12—13; Reply Br. 8—9. In particular, Appellants assert the
DEEPSLEEP and DEEPERSLEEP signals provide information about the
current CPU power state. App. Br. 12 (citing Park 4:50—53); Reply Br. 8.
Appellants contend the PSI of Crowther does not specify different non-zero
voltage levels. App. Br. 9. According to Appellants, because Crowther has
a goal of maintaining stable output voltage, the DEEPSLEEP and
DEEPERSLEEP signals in Park indicate different current draws. Reply Br.
8-9.
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Appeal 2015-007155
Application 13/120,652
In response, the Examiner finds DEEPSLEEP and DEEPERSLEEP
signals in Park control voltage levels provided to the CPU. Ans. 16—18.
The Examiner explains that each of the DEEPSLEEP and DEEPERSLEEP
signals has a high level that adjusts the CPU voltage to a particular level and
a low level that adjusts the CPU voltage to another level. Ans. 16 (citing
Park 5:4—60). We agree with the Examiner. Park teaches the
DEEPERSLEEP signal in a high level converts the CPU voltage to 0.85 V.
Park 2:3—10. Alternatively, Park teaches that a high DEEPSLEEP signal
converts the CPU voltage to 1.15—1.05 V. Park 2:32—36. When the
DEEPERSLEEP signal in Park is low, the CPU voltage is converted to
1.15—1.05 V. Park 5:19-25. Parks teachings contradict Appellants’
contention that the DEEPERSLEEP and DEEPSLEEP signals adjust CPU
power through voltage, not current. Reply Br. 8—9. Accordingly, we are not
persuaded of error in the Examiner’s obviousness rejection of claim 1.
Regarding claims 15 and 13, Appellants assert the DEEPSLEEP and
DEEPERSLEEP signals of Park do not specify the transition of voltage
levels of the power voltage to the processor. App. Br. 13, 14. Rather,
according to Appellants, the DEEPSLEEP and DEEPERSLEEP signals
indicate the current CPU power state. Id. In response, the Examiner finds
that when the DEEPERSLEEP signal is in high in level, it controls the
voltage to the CPU to be at the low power/sleep mode. Ans. 20. We agree
with the Examiner. Consistent with the discussion above, the
DEEPERSLEEP signal in Park reduces the CPU voltage from 1.2 V to 0.85
V. Park 5:40-45. Accordingly, we are not persuaded of error in the
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Appeal 2015-007155
Application 13/120,652
Examiner’s rejection of claims 15 and 13 based on Park and other
references.
Regarding the rejections of claims 2—9, 11—14, and 16—19, because
Appellants have presented no additional persuasive arguments (App. Br. 8,
10, 11, 13, 14, and 15; Reply Br. 6, 7, and 9), we sustain the rejections of
claims 2—9, 11—14, and 16—19.
DECISION
We affirm the Examiner’s rejections of claims 1—19.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F. R. § 1.136(a)(l)(iv).
AFFIRMED
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