Ex Parte Penton et al

Patent Trial and Appeal Board

Mar 26, 2014

12004476 (P.T.A.B. Mar. 26, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ANTONY JOHN PENTON,
ALEX JAMES WAUGH,
ANDREW CHRISTOPHER ROSE,
and PAUL STANLEY HUGHES
____________

Appeal 2011-013517
Application 12/004,476
Technology Center 2100
____________

Before ELENI MANTIS MERCADER, JAMES R. HUGHES, and
JEFFREY S. SMITH, Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2011-013517
Application 12/004,476

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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the rejection of
claims 1, 2, and 4-17. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse and enter new grounds of rejection.

Illustrative Claim
1. A data processing apparatus comprising:
a processing unit for performing data processing
operations;
cache storage for storing data values for access by the
processing unit when performing said data processing
operations, the cache storage comprising data storage having a
plurality of cache lines for storing data values, and address
storage having a plurality of entries, each entry identifying for
an associated cache line an address indication value, and each
entry having associated error data;
cache access circuitry, responsive to an access request
issued by the processing unit specifying an access address, to
perform a lookup procedure to determine with reference to the
address indication value held in at least one entry of the address
storage whether a hit condition exists in one of said cache lines;
error detection circuitry, responsive to the access request,
to determine with reference to the error data associated with
said at least one entry of the address storage whether an error
condition exists for that entry;
cache location avoid storage having at least one record,
each record for storing a cache line identifier identifying a
specific cache line;
on detection of said error condition, one of said at least
one records in the cache location avoid storage being allocated
to store the cache line identifier for the specific cache line
associated with the entry for which the error condition was
detected, the error detection circuitry causing a clean and
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invalidate operation to be performed in respect of the specific
cache line, and causing the access request to be re-performed;
the cache access circuitry excluding any specific cache
line identified in the cache location avoid storage from the
lookup procedure; and
allocation circuitry for allocating said one of the records
of the cache location avoid storage on detection of said error
condition, if every record of the cache location avoid storage
has an existing cache line identifier stored therein at the time
said error condition is detected, the allocation circuitry
invalidating one of said existing cache line identifiers to free
said one of the records to be allocated for storing the cache line
identifier for the specific cache line associated with the entry
for which the error condition was detected.

Prior Art
Smith US 3,781,796 Dec. 25, 1973
Ledbetter US 5,119,485 Jun. 2, 1992
Balkin US 5,835,504 Nov. 10, 1998
Walker US 6,539,503 B1 Mar. 25, 2003

Examiner’s Rejections
Claims 1, 2, 4, 7-10, and 12-17 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Balkin and Walker.
Claims 5 and 6 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Ledbetter.
Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Smith.

Appeal 2011-013517
Application 12/004,476

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ANALYSIS
Claim 1 recites “cache location avoid storage having at least one
record, each record for storing a cache line identifier identifying a specific
cache line.” The Examiner finds Balkin teaches storing defective cache line
addresses in redundant cache 12. Ans. 6. Appellants contend Balkin teaches
storing defective cache line addresses in registers in the processor, rather
than redundant cache 12. App. Br. 15-16; Reply Br. 7. In particular,
Appellants contend “to the extent [Balkin] stores any cache line identifier,
such identifier is stored in ‘registers in the processor’.” App. Br. 20.
We agree with Appellants that Balkin teaches addresses of the
defective cache lines stored in registers in the processor, and when a stored
address matches on a cache hit, a redundant line from the redundant cache is
substituted. Col. 2, ll. 11-14. Thus, we agree with Appellants that the
redundant cache 12, contrary to the Examiner’s finding (Ans. 6), does not
store defective cache line addresses. However, we find the registers storing
addresses of defective cache lines of Balkin teach the disputed limitation of
“cache location avoid storage having at least one record, each record for
storing a cache line identifier identifying a specific cache line” within the
meaning of claim 1.
Appellants further contend each tag stored in redundant cache 12 does
not store a cache line identifier identifying a specific cache line (App. Br.
16-20), but instead stores a portion of the memory address for a cache line
(Reply Br, 2-7). According to Appellants, the Examiner does not identify
any evidence that one of ordinary skill in the art would conclude that a cache
tag is a record storing a cache line identifier identifying a specific cache line.
Reply Br. 3.
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Balkin teaches a checker 13 that detects defective lines in cache 11.
The addresses of the defective lines are stored in registers in the processor,
and when a stored address is matched on a cache hit, a redundant line from
the redundant cache is substituted. Col. 2, ll. 10-14. Balkin further teaches
the redundant cache 12 has the same tag structure as cache structure 11.
Col. 2, ll. 29-31. Walker teaches a line of cache is identified by a tag that
includes the address of the line as is well known to those in the art. Col. 4,
ll. 39-43. We find one of ordinary skill in the art would have recognized that
each tag stored in redundant cache 12 of Balkin could have included the
entire address for the corresponding cache line as taught by Walker. The
redundant cache 12, when storing a tag including the entire address for a
corresponding cache line, or “cache line identifier,” as taught by Walker, is a
“cache location avoid storage” within the meaning of claim 1.
Appellants contend the combination of Balkin and Walker does not
teach allocation circuitry to invalidate an existing cache line identifier in the
cache location avoid storage to free a record to be allocated for storing a
more current cache line identifier. App. Br. 21-24; Reply Br. 8-13.
Appellants’ contention is based on the premise that the combination of
Balkin and Walker does not teach a cache location avoid storage, which we
find unpersuasive as discussed above. Further, Balkin teaches using a least
recently used algorithm to make room for storing more recent data in
memory. Col. 2, l. 31. Appellants have not provided persuasive evidence or
argument to show deleting data stored in memory, such as redundant cache
12, so that new data can be stored as taught by Balkin, was “uniquely
challenging or difficult for one of ordinary skill in the art.” Leapfrog
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Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
(citing KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 419 (2007)).
Appellants contend the Examiner did not articulate a reason to support
the legal conclusion that claim 1 is obvious. App. Br. 24-25; Reply Br. 13-
14. We find using the address of a cache line as a tag as taught by Walker in
a tag stored in redundant cache 12 of Balkin yields the predictable result of
“cache location avoid storage having at least one record, each record for
storing a cache line identifier identifying a specific cache line” as recited in
claim 1.
Because Balkin’s teaching of the processor registers storing addresses
of defective cache lines constitutes a new finding and because the Examiner
did not cite column 4 of Walker to teach a cache tag can include the entire
address of the cache line to identify a specific cache line, we reverse the
Examiner’s rejection and enter a new ground of rejection. Each of
independent claims 15, 16, and 17 contain a limitation similar to the “cache
location avoid storage” recited in claim 1 for which the rejection fails. We
reverse the Examiner’s rejections of claims 1, 2, and 4-17. We designate
new grounds of rejection, adopting the Examiner’s findings of fact from the
Examiner’s Answer, except as discussed above.
We reject claims 1, 2, 4, 7-10, and 12-17 under 35 U.S.C. § 103(a) as
being unpatentable over Balkin and Walker.
We reject claims 5 and 6 under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Ledbetter.
We reject claim 11 under 35 U.S.C. § 103(a) as being unpatentable
over Balkin, Walker, and Smith.

Appeal 2011-013517
Application 12/004,476

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DECISION
The rejection of claims 1, 2, 4, 7-10, and 12-17 under 35 U.S.C.
§ 103(a) as being unpatentable over Balkin and Walker is reversed.
The rejection of claims 5 and 6 under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Ledbetter is reversed.
The rejection of claim 11 under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Smith is reversed.
We reject claims 1, 2, 4, 7-10, and 12-17 under 35 U.S.C. § 103(a) as
being unpatentable over Balkin and Walker.
We reject claims 5 and 6 under 35 U.S.C. § 103(a) as being
unpatentable over Balkin, Walker, and Ledbetter.
We reject claim 11 under 35 U.S.C. § 103(a) as being unpatentable
over Balkin, Walker, and Smith.
This decision contains new grounds of rejection pursuant to 37 C.F.R.
§ 41.50(b) (2011). Section 41.50(b) provides that “[a] new ground of
rejection . . . shall not be considered final for judicial review.”
Section 41.50(b) also provides that Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner. . . .

(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same record.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

REVERSED
37 C.F.R. § 41.50(b)

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