Ex Parte Pennock et al

Patent Trial and Appeal Board

Feb 4, 2013

11771764 (P.T.A.B. Feb. 4, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/771,764 06/29/2007 James D. Pennock HARM0154PUSP 8473
109676 7590 02/05/2013
Brooks Kushman P.C./Harman
1000 Town Center
Twenty Second Floor
Southfield, MI 48075
EXAMINER
HASSAN, AURANGZEB
ART UNIT PAPER NUMBER
2184
MAIL DATE DELIVERY MODE
02/05/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte JAMES D. PENNOCK, RONALD BAKER,
BRIAN R. PARKER, and CHRISTOPHER BELCHER
_____________

Appeal 2011-001738
Application 11/771,764
Technology Center 2100
______________

Before ROBERT E. NAPPI, HUNG H. BUI, and LYNNE E. PETTIGREW,
Administrative Patent Judges.

ROBERT E. NAPPI, Administrative Patent Judge

DECISION ON APPEAL
Appeal 2011-001738
Application 11/771,764

2

This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1 through 12, 14, 15, and 17 through 24.

We affirm.
INVENTION
The invention is directed to a communications interface which
includes a set of memory spaces which alternately interface with a processor
or a serial controller. See paragraphs 0007-0009 of Appellants’
Specification. Claim 1 is representative of the invention and reproduced
below:
1. An external memory interface engine, comprising:
a processor;
a memory control subsystem comprising multiple
programmable external memory control bits that specify an
access operation of multiple different types of external
memories;
a memory control subsystem comprising:
a first memory shared between the processor and
the memory control subsystem;
a second memory shared between the processor
and the memory control subsystem; and
a swap controller configured to alternately couple the
first memory and the second memory between the processor
and the memory control subsystem,
where the memory control subsystem is configured to
analyze control information and address information stored in
the memory subsystem and responsively output the
programmable external memory control bits.

Appeal 2011-001738
Application 11/771,764

3

REJECTIONS AT ISSUE
The Examiner has rejected claims 1 through 3, 5 through 12, 14, 15,
17, and 18 under 35 U.S.C. § 103(a) as unpatentable over Yoshimura (U.S.
Patent 6,421,274 B1) and Keltcher (U.S. Patent 7,043,679 B1). Answer 4-
5.
1

The Examiner has rejected claims 4 and 19 through 24 under 35
U.S.C. § 103(a) as unpatentable over Yoshimura, Keltcher, and Hall (U.S.
Patent 5,581,779). Answer 8-9.

ISSUE
Appellants argue on pages 9 through 11 of the Appeal Brief that the
Examiner’s rejection of claims 1 through 3, 5 through 12, 14, 15, 17 and 18
under 35 U.S.C. § 103(a) is in error.
2
These arguments present us with the
issue: did the Examiner err in finding that Yoshimura teaches a controller to
alternatively swap access to the first buffer memory and the second buffer
memory between the processor and communications subsystem as recited in
representative claim 1?
Appellants’ argue on pages 11 and 12 of the Brief that the rejection
under 35 U.S.C. § 103(a) based upon Yoshimura, Keltcher, and Hall is in
error for the same reason as discussed with respect to claim 1. Accordingly,
Appellants’ arguments directed to the Examiner’s rejection under 35 U.S.C.
§ 103(a) does not present us with any additional issues.

1
Throughout this opinion we refer to the Examiner’s Answer mailed on
July 22, 2010.
2
Throughout this opinion we refer to Appellants’ Appeal Brief filed on
May 12, 2010.
Appeal 2011-001738
Application 11/771,764

4

ANALYSIS
We have reviewed Appellants’ arguments in the Brief, the Examiner’s
rejection and the Examiner’s response to the Appellants’ arguments. We
disagree with Appellants’ conclusion that the Examiner erred in finding that
Yoshimura teaches a controller to alternatively swap access to the first
buffer memory and the second buffer memory between the processor and
communications subsystem. The Examiner has provided a comprehensive
response to this issue in the Answer. In particular, the Examiner has found
that Yoshimura teaches two memory locations R1 and R2 (see Figure 1)
which are alternately connected to a processor or a memory control
subsystem. Answer 9-10.
We concur with the Examiner’s findings and note that Figures 2A,
2B, 7A, 7B and the accompanying text in Yoshimura provide an example of
the alternate access to the memory locations R1 and R2. Based upon these
findings, the Examiner concludes that the argued limitation is taught by
Yoshimura. We concur with the Examiner’s conclusions in the Answer and
adopt them as our own. Accordingly, we sustain the Examiner’s rejections
under 35 U.S.C. § 103(a).

ORDER
The decision of the Examiner to reject claims 1 through 12, 14, 15,
and 17 through 24 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

Appeal 2011-001738
Application 11/771,764

5

AFFIRMED

ELD