Ex Parte Pendse

Patent Trial and Appeal Board

Sep 29, 2017

13965356 (P.T.A.B. Sep. 29, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/965,356 08/13/2013 Rajendra D. Pendse 2515.0037 CON6 5320
112165 7590 10/03/2017
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
EXAMINER
LEE, HSIEN MING
ART UNIT PAPER NUMBER
2823
NOTIFICATION DATE DELIVERY MODE
10/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL
AND APPEAL BOARD
Ex parte RAJENDRA D. PENDSE
Appeal 2017-0008731
Application 13/965,356
Technology Center 2800
Before MICHAEL P. COLAIANNI, JEFFREY B. ROBERTSON, and
MICHAEL G. McMANUS, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
1 The real party in interest as indicated in the Appeal Brief is “STATS
ChipPAC, Ltd.”
Appeal 2017-000873
Application 13/965,356
Appellant appeals under 35 U.S.C. § 134 the final rejection of claims
7—25. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b).
Claims 34—36 are objected to as being dependent upon a rejected base claim
but would be allowable if written in independent form including all the
limitations of the base claim and are not on appeal. (Final Act. 13).
We AFFIRM.
Appellant’s invention is directed to a flip chip interconnection in a
semiconductor package and a method of manufacturing (Spec. 12).
Claim 7 is illustrative:
7. A method of making a semiconductor device, comprising:
providing a substrate [312];
forming a trace [355] including an interconnect site over a
surface of the substrate; and
forming a composite interconnect structure including a
collapsible portion [347] and a non-collapsible portion [345]; and
disposing the composite interconnect structure over the
interconnect site of the trace.
Bracketed reference numerals were added to map the claim limitations to
Appellant’s Figure 13.
Appellant appeals the following rejections:
1. Claims 7—10, 12, 14—17, 19, 21, 22, and 24 are rejected 35 U.S.C.
§ 102(b) as anticipated by Bentlage (US 5,798,285, pat. Aug. 25,
1998).
2. Claims 14, 17, and 19 are rejected under 35 U.S.C. § 102(a) as
anticipated by Yeh (US 2004/0035909 Al, pub. Feb. 26, 2004).
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Application 13/965,356
3. Claims 11, 13, 18, 20, 23, and 25 are rejected under 35 U.S.C. §
103(a) as unpatentable over Bentlage in view of Lin (US
2004/0126927 Al, pub. Jul. 1, 2004).
4. Claims 15 and 16 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Yeh in view of Smith (US 2002/0041036 Al, pub.
Apr. 11,2002).
5. Claims 18 and 20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Yeh in view of Lin.
Appellant’s arguments focus on subject matter in independent claims
7, 14, and 21 and dependent claim 8 (Br. 6-13). Rejections (3) to (5) under
35 U.S.C. § 103(a) are not separately argued (App. Br. 14). Accordingly,
the claims under rejections (3) to (5) will stand or fall with our analysis of
the argued claims under the § 102 rejections.
FINDINGS OF FACT & ANALYSIS
CLAIM 7
The Examiner finds that Bentlage teaches the subject matter of claim
7 including forming a composite interconnect structure including a
collapsible portion and a non-collapsible portion and disposing the
composite interconnect structure over the interconnect site of the trace (Final
Act. 3—4). The Examiner finds that Bentlage teaches disposing the
composite interconnect structure 36 over the interconnect site 60 of the trace
24 when contacting both the substrate 22 with the collapsible portion 38 and
a chip 26 with the non-collapsible portion 37 followed by a reflow process
(Final Act. 4; see Bentlage, Fig. 11). The Examiner finds that Bentlage
teaches contacting solder bump 37 (C4) with solder bump 38 and then
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Application 13/965,356
reflowing the solder to form the solder joint (i.e., a two-step technique)
(Ans. 4). The Examiner finds that claim 7 does not exclude Bentlage’s
“two-step technique” for forming a composite interconnect structure (Ans.
4).
Appellant argues that neither Bentlage’s C4 solder bump 37 nor solder
bump 38 are, themselves, a composite interconnect structure (Br. 7).
Appellant argues that solder bumps 37 and 38 are not formed into solder
joint 36 prior to disposing solder joint 36 over nickel layer 60 (Br. 7).
Claim 7 recites “forming a composite interconnect structure including
a collapsible portion and a non-collapsible portion; and disposing the
composite interconnect structure over the interconnect structure over the
interconnect site of the trace.” Appellant contends that claim 7 requires that
the composite interconnect structure is formed first and then disposed over
the interconnect site of the trace. Appellant’s claim construction reads
limitations into the claim. Claim 7 does not require separately forming the
composite interconnect structure and subsequently disposing the composite
interconnect structure over the interconnect site of the trace as argued.
Rather, the Examiner reasonably finds that the broadest reasonable
interpretation of claim 7 includes Bentlage’s forming a portion of the
composite solder (i.e., C4) on the chip 26 and a second portion (i.e., solder
bump 38) of the composite solder on the substrate carrier disposed over the
copper line trace to form solder joint 36 disposed over the interconnect site
of the trace (Bentlage, Figs. 5 and 11). The solder joint 36 composed of
solder bump C4 and solder bump 38 is formed and disposed over the
interconnect site of the trace. Claim 7 is not as limited as Appellant has
argued.
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Appeal 2017-000873
Application 13/965,356
We affirm the Examiner’s § 102(b) rejection of claim 7.
CLAIM 8
Appellant argues that Bentlage does not teach forming an insulating
layer including an opening disposed over the interconnect site of the trace
(Br. 8). Appellant argues that Bentlage’s encapsulant does not include an
opening formed in it above the interconnection site (Br. 8). Appellant
contends that one skilled in the art would not consider an encapsulant
formed around solder joint 36 with no voids as being an insulating layer
including an opening over an interconnect site (Br. 8).
The Examiner finds that Bentlage teaches forming an encapsulant
around the solder joint 36 (i.e., interconnect structure) (Final Act. 4; Ans. 7;
Bentlage Figs. 5, 11). The Examiner finds that the opening in the
encapsulant is the open space above the conductive trace where the
interconnect structure resides. Id. In other words, the Examiner finds that
the solder joint 36 location corresponds to an opening filled by solder and
surrounded by encapsulant.
Claim 8 does not recite at what point during the method an insulating
layer including an opening disposed over the interconnect site over the trace
is formed. Accordingly, under the broadest reasonable interpretation of the
claim, the opening in the insulating layer may be formed at any point during
the method, which may include forming the opening after forming the solder
joint 36. In other words, an opening filled with solder over an interconnect
site on a trace is not excluded by the claim.
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Application 13/965,356
Moreover, Bentlage teaches that it is known to form a soldermask
layer over the circuit lines except for the chip/solder sites (Bentlage, col. 2,
11. 40-41; col. 4,11. 63—64; col. 5,11. 16—19; Fig. 8, ref. no. 56). Bentlage’s
soldermask corresponds to an insulating layer that has openings above the
chip/solder sites.
On this record, we affirm the Examiner’s § 102(b) rejection of claim 8
over Bentlage.
CLAIM 14
Appellant argues that Bentlage does not teach an interconnect
structure disposed directly on the interconnect site of the trace and including
a width greater than a width of the interconnect site of the trace (Br. 9).
Appellant contends that Bentlage’s oxidized nickel layer 60 on the surface of
the copper trace shows that the solder layer is not disposed directly on the
copper circuit lines 24 (Br. 9-10). Appellant further argues that Bentlage
does not disclose the width of the solder bump as compared to the width of
the trace line (Br. 10).
Regarding the § 102(a) rejection over Yeh, Appellant argues that
Yeh’s disclosure regarding copper trace 18 is insufficient to anticipate the
subject matter of claim 14 (Br. 11). Appellant contends that Yeh does not
disclose the width of the trace 18 and contains no disclosure as to an
interconnect structure disposed directly on the interconnect site of the trace
(Br. 11).
The Examiner finds that Bentlage teaches that the solder bump is
directly disposed on the interconnect site because no other layer is disposed
between the interconnect structure 36 and the interconnect site (Final
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Application 13/965,356
Act. 7). The Examiner also finds that Bentlage in Figure 5 shows that the
solder bump 36 is wider than the width of the trace 24 (Final Act. 6).
Regarding Yeh, the Examiner finds that Yeh’s Figure 1 shows that the
interconnect structure 12 is disposed directly on the interconnect site of the
trace 18 and includes a width W greater than the width w of the interconnect
site trace 18 (Final Act. 9).
The Examiner’s rejections over Bentlage and Yeh are based on the
relative size of the solder bump and the trace. The Examiner relies on
Bentlage’s and Yeh’s figures to show that the relative dimension of the
solder bump is wider than the width of the trace. We are unpersuaded by
Appellant’s argument that the figures are insufficient to establish the width
of the solder bump as compared to the width of the trace. The Examiner
may rely on figures or drawings in a patent that clearly show the structure
that is claimed. In re Mraz, 455 F.2d 1069, 1072 (CCPA 1972). In this
case, the figures in Bentlage and Yeh clearly show that the relative width of
solder bump is wider than the width of the trace. Therefore, the Examiner
did not reversibly err in finding that Bentlage and Yeh teach the relative
widths of the trace and solder bump.
We are unpersuaded by Appellant’s argument that Bentlage’s
oxidized layer 60 on the trace prevents the solder bump from being directly
disposed on the interconnect site. The Examiner relies on Bentlage’s
disclosure regarding Figure 5, which does not include an oxidized layer 60
as in Figure 11 (Ans. 9). Appellant has not shown reversible error with the
Examiner’s stated rejection (Final Act. 6-7).
Nevertheless, we fail to see how an oxidized nickel layer on the
surface of the trace in Bentlage’s Figure 11 would prevent a solder bump
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from being directly disposed on the trace. The oxidized nickel surface on
the trace becomes part of the trace. Accordingly, the solder bump 36 is
directly formed on the trace that includes the oxidized nickel layer. Claim
14 does not preclude having additional layers be part of the interconnect site
of the trace.
On this record, we affirm the § 102 rejections of claim 14 over
Bentlage and Yeh.
CLAIM 21
Appellant argues that Bentlage does not teach a trace formed over the
substrate and a composite interconnect structure deformed over an
interconnect site of the trace (Br. 12). Appellant contends that Bentlage
does not disclose that solder joint 36 is deformed over circuit line 24. Id.
Appellant contends that Bentlage teaches thermally reflowing the solder but
does not teach mechanically deforming a composite interconnect structure
over an interconnect site (Br. 13).
The Examiner correctly finds that claim 21 does not limit the type of
deformation (Ans. 13). Therefore, Bentlage’s thermal deformation of the
solder joint is sufficient to meet the claim. No mechanical deformation is
necessary to satisfy the claim language.
On this record, we affirm the Examiner’s § 102 rejection of claim 21.
For the above reasons, we affirm the Examiner’s following rejections:
(1) § 102(b) rejection over Bentlage, (2) § 102(a) rejection over Yeh, (3) §
103(a) rejection over Bentlage in view of Lin, (4) § 103(a) rejection over
Yeh in view of Smith, and (5) § 103(a) rejection over Yeh in view of Lin.
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DECISION
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
ORDER
AFFIRMED
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