Ex Parte Pelley et al

Patent Trial and Appeal Board

Sep 29, 2017

14525347 (P.T.A.B. Sep. 29, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/525,347 10/28/2014 Perry H. Pelley 1080-DN30844TK 2874
114905 7590
NXP-Davidson Sheehan
6501 William Cannon Drive West
Austin, TX 78735
EXAMINER
MANDALA, MICHELLE
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
10/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PERRY H. PELLEY,
MICHAEL B. McSHANE, and TIM V. PHAM
Appeal 2017-002812
Application 14/525,3471
Technology Center 2800
Before ADRIENE LEPIANE HANLON, KAREN M. HASTINGS, and
DONNA M. PRAISS, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellants filed an appeal under 35 U.S.C. § 134 from an Examiner’s
decision finally rejecting claims 1—10 and 21. Claims 11—20 are also pending but
have been withdrawn from consideration. We have jurisdiction under 35 U.S.C.
§ 6(b).
We REVERSE.
1 According to the Appellants, the real party in interest is Freescale Semiconductor,
Inc. Appeal Brief dated August 8, 2016 (“App. Br.”), at 1.
Appeal 2017-002812
Application 14/525,347
Representative claims 1 and 10 are reproduced below from the Claims
Appendix. The limitations at issue are italicized.
1. An integrated circuit device, comprising:
a die address bus;
a plurality of dies arranged in a stacked die integrated circuit,
the plurality of dies comprising a first die including:
a storage location configured to store information
indicating a width of the die address bus; and
an interface configured to receive a die address via the
die address bus based on the information.
App. Br. 9.
10. An integrated circuit device, comprising:
a plurality of stacked die comprising a first die and a second
die; and
a data bus having a width based on the first die being disposed
on the stack in a first orientation of a plurality of possible orientations
and the second die being disposed on the stack in a second orientation
of the plurality of orientations.
App. Br. 10-11.
The Examiner maintains the following rejections on appeal:
(1) claims 1,9, and 21 under 35 U.S.C. § 103(a) as unpatentable over
Ide;2 and
(2) claims 2—8 and 10 under 35 U.S.C. § 103(a) as unpatentable over Ide
in view of Foster, Sr. et al.3
B. DISCUSSION
1. Claims 1 and 21
2 US 2012/0134193 Al, published May 31, 2012 (“Ide”).
3 US 2011/0109381 Al, published May 12, 2011 (“Foster”).
2
Appeal 2017-002812
Application 14/525,347
The Examiner finds Ide discloses an integrated circuit device comprising a
die address bus and a plurality of dies arranged in a stacked die integrated circuit
(Ide Fig. 10, CC0-CC7) wherein a first die (e.g., CC7 or CCO) includes a storage
location (43, SID) and an interface (41, access control circuit). Final 4.4 The
Examiner finds:
In reference to the claim language referring to the function of the
device, i.e., “a storage location [configured] to store information
indicating a width of the die address bus” and “an interface configured
to receive a die address via the die address bus based on the
information”, the device of Ide is capable of performing said
functions. For example, the SID (43) of Ide contains a chip address
register (|0048) but could also be programmed to contain information
about the width of the die address bus (see e.g. 10049, programming
the SID using TSVs).
Final 5 (emphasis added).
The Appellants argue that in In re Gianelli, 739 F.3d 1375 (Fed. Cir. 2014),
the Court “held that the term ‘configured to’ ... in a device claim requires that the
device be designed or constructed to be able to perform the recited features.” App.
Br. 3^4 (emphasis omitted). In this case, the Appellants argue that the Examiner
“has failed to show that it is obvious to modify [the] storage location and interface
of Ide to correspond to the [limitation at issue] of claim 1.” App. Br. 4.
According to the Examiner:
[I]t is well-known in the art that a common method of addressing dies
is to split the full address into two (or more) pieces, which are
delivered throughout the time cycle of an operation. For example, a
full 32-bit address may be chopped into two pieces, each piece being
transmitted through a 16-line bus [i.e., n address width], and the two
pieces being recombined by the die interface to form the full address
[i.e., 2n address width] for an operation. This addressing scheme is
nearly ubiquitous in large-memory applications because it allows the
4 Final Office Action dated December 11, 2015.
3
Appeal 2017-002812
Application 14/525,347
transmission of full addresses (with a 2n address width) through far
fewer bus lines; therefore, the address bus of a device does not have to
have n lines, which reduces manufacturing costs associated with
creating larger and larger bus sizes. However, for such an addressing
system to work, the receiving interface (e.g. 41 in Ide) must have
information determining the size of the full die address and the die
address bus in order to properly determine the intended address being
transmitted by the die address bus. Thus, it would have been obvious
to one of ordinary skill in the art to modify Ide with information
indicating a width of the die address bus, as described in the rejection
of claim 1 . . . .
Final 2 (original emphasis omitted); see also Ans. 5.5
The Appellants argue:
[T]he Office provides no support for this assertion, and has therefore
failed to establish a prima facie showing of obviousness for claim 1.
Further, even assuming arguendo that the assertion is correct, the
mere fact that a die may receive a full address in two or more pieces
does not teach “a storage location configured to store information
indicating a width of the die address bus . . .” as provided by claim 1.
That is, a die can receive a full address in two or more pieces without
employing a storage location configured to store information
indicating a width of the die address bus .... For example, assuming
a die employs a fixed 16-bit address bus that receives a 32-bit address
in two pieces, the die would have no need to employ a storage
location indicating the width of the die address bus, as the width of
the address bus is fixed and it receives the 32-bit address according to
a regular pattern.
App. Br. 5 (emphasis added). The Appellants argue that “under the system taught
by Ide, the number of bits used to address a given die remains fixed, so it would
not be obvious to program a chip address register to contain information about the
width of the die address bus.” Reply Br. 3.6
5 Examiner’s Answer dated October 21, 2016.
6 Reply Brief dated December 20, 2016.
4
Appeal 2017-002812
Application 14/525,347
The Appellants’ argument is persuasive of reversible error. We recognize
that SID (or chip address register) 43 (corresponding to the claimed storage
location) could have been programmed to store information about the width of the
die address bus, as found by the Examiner. The Examiner, however, has failed to
show that the width of Ide’s die address bus is not fixed as the Appellants contend.
Thus, absent the Appellants’ disclosure, it is not readily apparent on this record
why one of ordinary skill in the art would have programmed SID (or chip address
register) 43 with information indicating a width of the die address bus. For that
reason, the § 103(a) rejection of claims 1, 9, and 21 based on Ide is not sustained.
The Examiner does not rely on Foster to cure the deficiency in the § 103(a)
rejection based on Ide. Therefore, the § 103(a) rejection of claims 2—8 is not
sustained.
2. Claim 10
The Examiner finds Ide does not disclose “a data bus having a width based
on the first die being disposed on the stack in a first orientation of a plurality of
possible orientation[s] and the second die being disposed on the stack in a second
orientation of the plurality of orientations” as recited in claim 10. Final 10. The
Examiner, however, finds:
Foster teaches an integrated circuit die stack with two types (28 and
30) of symmetrically disposed vias. Die 102 of Fig. 3 comprises a
first set (30) of through silicon vias (TSVs) which also connect to
electronic circuitry of the die and a second set (28) of pass-through
(PTVs) which simply pass through the die without connecting to
circuitry in the die (see 10019).
Final 10.
The Examiner finds:
Taking Ide in view of Foster, a memory stack is taught in which the
orientation of the chips (Fig. 3, dies 102—108) will affect the width of
5
Appeal 2017-002812
Application 14/525,347
the data bus. For instance, if die 108 is placed directly on die 102,
data bus lines are required for the circuitry of both dies. However, if
die 108 is flipped along a body diagonal and placed over die 102,
then data bus [width] is not required for the PTV vias (which contain
no information), so the data bus width is halved. In this case, the
width of the data bus is a natural extension of the orientations of the
two dies.
Final 10-11 (emphasis added).
The Appellants argue that “Foster teaches that dies are to be oriented to
create connections between the dies, but does not teach or suggest that the
orientation of the dies establish a bus width.” App. Br. 7. Moreover, the
Appellants argue that “the [Examiner’s] rejection of claim 10 is premised on a
theoretical arrangement of dies that is not actually disclosed or suggested by
Foster.” App. Br. 7. More specifically, the Appellants argue:
Foster teaches that “the TSVs (30) and PTVs (28) are disposed upon
each identical die so that the positions of the TSVs and PTVs on each
identical die are rotationally symmetrical with respect to the TSVs and
PTVs on the other identical die. . . . That is, the TSVs and PTVs are
disposed upon each identical die so that TSVs align with PTVs when
one die is rotated 90 degrees in a same plane with respect to any
other identical die.” (See, e.g., Foster para. [0026]). Thus, not only is
the hypothetical arrangement of “consistently stacking” identical dies
in the same orientation proposed by the Examiner not disclosed or
suggested by Foster, it is inconsistent with the teaching of Foster that
the dies are stacked so that each die is rotated with respect to the dies
with which it connects so that TSVs align with PTVs.
Reply Br. 4 (emphasis added).
The Appellants’ argument is persuasive of reversible error. Foster discloses
that each of dies 102, 104, 106, and 108 in Foster Figure 3 are identical. See Foster
126 (“[a]ll four dies in the example of FIG. 3 are identical”). Moreover, Foster
discloses that each of dies 102, 104, 106, and 108 in a die stack are rotated relative
to the previously stacked die, i.e., die 104 is rotated 90 degrees relative to die 102,
6
Appeal 2017-002812
Application 14/525,347
die 106 is rotated 90 degrees relative to die 104, and die 108 is rotated 90 degrees
relative to die 106. Foster 127.
We recognize that Foster discloses another embodiment wherein two or
more identical dies, forming a first substack, are stacked upon one another without
rotation with respect to one another. Foster 146. In that embodiment, however, a
second substack (i.e., two or more identical dies stacked upon one another without
rotation with respect to one another) is rotated with respect to the first substack and
then mounted thereon. Foster 147.
On this record, the Examiner has failed to show that the die orientations
disclosed in Foster establish a bus width. For that reason, the § 103(a) rejection of
claim 10 based on the combination of Ide and Foster is not sustained.
C. DECISION
The Examiner’s decision is reversed.
REVERSED
7