Ex Parte Pawlowski

Patent Trial and Appeal Board

Aug 13, 2018

12350136 (P.T.A.B. Aug. 13, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/350, 136 01/07/2009 J. Thomas Pawlowski
52142 7590 08/15/2018
FLETCHER YODER (MICRON TECHNOLOGY, INC.)
P.O. BOX 692289
HOUSTON, TX 77269-2289
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2008-0377 (MICS:0277) 6331
EXAMINER
VO,TIMT
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
08/15/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@fyiplaw.com
manware@fyiplaw.com
s trickland @fyiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte J. THOMAS PA WLOWSKI 1
Appeal2017-002885
Application 12/350, 136
Technology Center 2100
Before CAROLYN D. THOMAS, JOHNNY A. KUMAR, and
JON M. JURGOV AN, Administrative Patent Judges.
JURGOV AN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant seeks review under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1-13 and 45-57, constituting the only claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm. 2
1 According to Appellant, the real party in interest is Micron Technology,
Inc .. See Appeal Br. 2.
2 Our Decision refers to the Specification ("Spec.") filed January 7, 2009,
the Final Office Action ("Final Act.") mailed January 20, 2016, the Appeal
Brief ("App. Br.") filed June 27, 2016, the Examiner's Answer ("Ans.")
mailed October 20, 2016, and the Reply Brief ("Reply Br.") filed December
19, 2016.
Appeal2017-002885
Application 12/350, 136
CLAIMED INVENTION
The claims are directed to systems with a processing unit connected to
a pattern-recognition processor and memory by independent buses. Spec.
,r 70, Fig. 13. A first portion of common signals on the buses are interpreted
by the pattern-recognition processor and memory to perform the same
function, and a second portion of the common signals on the buses are
interpreted by the pattern-recognition processor and memory to serve a
different function. Spec. ,r,r 76, 78-79, Abstract. Claim 1, which is
representative of the claimed invention, is reproduced below:
1. A system, comprising:
a pattern-recognition processor;
a processing unit (PU) coupled to the pattern-recognition
processor via a pattern-recognition bus; and
memory coupled to the PU via a memory bus physically
independent from the pattern-recognition bus, wherein the pattern-
recognition bus and the memory bus form about the same number of
connections to the pattern-recognition processor and the memory,
respectively, and wherein a portion of the pattern-recognition bus
serves at least one different function compared to a corresponding
portion of the memory bus, wherein the pattern-recognition processor
and the memory are configured to interpret at least a first portion of
common signals received, respectively, over the pattern-recognition
bus and over the memory bus to serve a same function, wherein the
pattern-recognition processor and the memory are configured to
interpret at least a second portion of the common signals received,
respectively, over the pattern-recognition bus and over the memory
bus to serve a different function.
App. Br. ("Claims App.").
2
Appeal2017-002885
Application 12/350, 136
REJECTIONS
Claims 1---6, 8-11, 13, and 45--47 stand rejected under 35 U.S.C.
§ I03(a) based on Arnold (US 6,279,128 Bl, issued Aug. 21, 2001) and
Chesson (US 5,524,250, issued June 4, 1996). Final Act. 2-17.
Claim 7 stand rejected under 35 U.S.C. § I03(a) based on Arnold,
Chesson, and "well-known prior art." Final Act. 17-18.
Claim 12 stands rejected under 35 U.S.C. § I03(a) based on Arnold,
Chesson, and "well-known prior art." Final Act. 18-19.
ANALYSIS
§ 103 Rejections
Claim 1
Claim 1 recites "wherein the pattern-recognition processor and the
memory are configured to interpret at least a first portion of common
signals received, respectively, over the pattern-recognition bus and over
the memory bus to serve a same function." See claim 1, supra. (emphasis
added). Appellant argues Arnold fails to render this feature obvious. App.
Br. 5-1 O; Reply Br. 2---6. Specifically, Appellant argues "Arnold does not
appear to teach that common signals received at memory 18 and data pattern
monitor 12 are interpreted to serve a same function at each of the memory
18 and the data pattern monitor 12." App. Br. 7. Appellant argues Arnold's
autonomous memory scrubbing process performed by scrub sequencer 32,
and data pattern monitoring function performed by data pattern monitor 12,
in conjunction with controller 20 and memory 18, do not perform the same
function, but different functions. App. Br. 6-7. These features are shown
below in Figures 1 and 2 of Arnold.
3
Appeal2017-002885
Application 12/350, 136
20 32
f SCRUB
CONTROLLER ---..- SEQUENCER
MEMORY
m DATA
PATTERN
MONITOR
12
FIG. 1
10
14 I
CONTROLLER
DASO
~
16
Figure 1 of Arnold shows CPU 14 and controller 20 connected to bus 16, as
well as memory 18, data pattern monitor 12, and scrub sequencer 32, which
are connected to controller 20.
FIG. 2
DATA PATTERN
MONITOR
12
""-
<(· 20
1~oLATEo 02i-----!,TARGET MEMORY
! LOAD£R.
Figure 2 of Arnold shows data pattern monitor 12 and memory 18 connected
to control (C) bus 66, address (A) bus 68, and data (DI) bus 56, along with
scrub sequencer 32 and error detection and correction circuitry for
performing a scrub cycle.
4
Appeal2017-002885
Application 12/350, 136
We disagree with Appellant's argument. As the Examiner found, the
"same function" limitation is disclosed by Arnold's pattern-recognition
processor 12 and memory 18 receiving the same address, command, and
data signals on bus lines 66, 68, and 56. Final Act. 8-9 (citing Arnold 6:31-
34; see also 6: 19-30, Fig. 2). The pattern-recognition processor 12 and
memory 18 interpret3 the same received signals as an address, command,
and data.
As to the "different function" and "first portion" and "second portion
of common signals" limitations, the Examiner also found concerning Arnold
the portion of the pattern recognition bus serves at least one different
function [i.e., detecting and recognizing a data bit pattern(s) from the
data signal on the internal bus 56 between the data pattern monitor 12
and CPU 14 (Fig. 1)] compared to a corresponding portion of the
memory bus [the internal bus 56 of the standard DRAM memory bus
used for a memory operation, i.e., transferring data signal between the
DRAM memory 18 and the CPU 14 (Fig. 1)].
Ans. 13 ( quoting Final Act. 5-6 with the Examiner's edits). Thus, the
Examiner is not relying on the functions of the scrub sequencer 32 and data
pattern monitor 12 to teach the "different functions" limitation, as Appellant
assumes, but instead relies on detecting and recognizing a data bit pattern,
and transferring data signals in a memory operation, as the "different
functions." The "first portion" and "second portion of common signals" are
the portions of the same common signals on the pattern recognition bus and
memory bus, respectively. As Appellant's arguments do not address the
3 Appellant may assume the word "interpret" means the receiving unit must
be able to process the same signal in different ways, but no such meaning is
provided for the term in the Specification or set forth in the claims.
5
Appeal2017-002885
Application 12/350, 136
rejection as applied, we find Appellant's argument unpersuasive to show
Examiner error.
Appellant also notes that claim 1 recites the memory bus is
"physically independent from the pattern-recognition bus." App. Br. 5-
6, 9. ( emphasis added). Appellant does not argue that Chesson fails to teach
or suggest this feature, but instead questions whether Arnold could be
modified by Chesson to include a memory bus that is physically independent
from a pattern-recognition bus. Id. However, Appellant offers no
explanation why Arnold could not be so modified by Chesson. This kind of
argument is not persuasive to show Examiner error. See 37 C.F.R.
§ 4I.37(c)(l)(iv) ("The arguments shall explain why the examiner erred as
to each ground of rejection contested by appellant." (emphasis added)).
Appellant further argues that Arnold's control words and physical
addresses are not used by the data pattern monitor 12 to access data words,
as they are in the memory 18. Reply Br. 3. Again, the "same function"
identified by the Examiner is not the accessing of data words, but the
receiving of the address, control, and data signals on bus lines 66, 68, and
56, which is performed by both data pattern monitor 12 and the memory 18.
Final Act. 8-9 (citing Arnold 6:31-34; see also 6:19-30, Fig. 2). Thus,
Appellant's argument is not persuasive.
Appellant also contends the Examiner provided no citation in Arnold
as evidence that control words provide timing and operations for the data
words of the data pattern monitor 12. Reply Br. 4. We note the Examiner
relied on the receiving of the address, control, and data signals as evidence
of the "same function" performed by the data pattern monitor 12 and
6
Appeal2017-002885
Application 12/350, 136
memory 18 in Arnold. Final Act. 8-9. Accordingly, Appellant's argument
is not persuasive.
Claim 2
Claim 2 recites "the pattern recognition bus forms at least one
more connection than the memory bus." App. Br. ("Claims App.").
(emphasis added). Appellant argues the Examiner relied on Arnold's
internal bus 90 as teaching this limitation, but because this bus is distinct
from internal buses 56, 66, and 68, the connections on internal bus 90 are
irrelevant to teaching a pattern recognition bus that forms at least one more
connection than the memory bus, as recited in claim 2. App. Br. 10-11.
Furthermore, Appellant argues the Examiner has not indicated the numbers
of connections each of these buses have, and thus could not have determined
that the claim limitation is taught or suggested in Arnold. Id. Arnold's
Figure 3 is shown below to provide context for the argument.
[j] C
,_£68 66
I MO~ITOR
I coi,iwoLLER
I m
, .. _J--110
i
i
i
i lNTERRIJf'T
]GENERATOR
!
j ~§
r-9~ I
I L
1
_1
CLEAN
WINDOW
!LOG TASLE
92
._aa , ____ L __
i SIGNATURE
1 jCOMPAR1SON
I : 78 {. -
84
THRESHOLD
FIG. 3
~ ~S6
_j~J:::n
CODE
S.:ONATURE
COMPUTATION
r-.11.
j
-·········-·_J
We do not agree with Appellant's arguments. Claim terms are given
their broadest reasonable interpretation consistent with the Specification. In
7
Appeal2017-002885
Application 12/350, 136
re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004).
Given its breadth, claim 2' s limitation could be interpreted as meaning that
the pattern recognition bus has an additional connection the memory bus
does not have, namely, the connection of the internal bus 66 to the internal
bus 90, as found by the Examiner. Final Act. 12-13 ( citing Arnold 7 :4 7-
58). The Specification provides no definition or meaning which would
preclude the Examiner's broad, but reasonable, interpretation of the claimed
phrase "forms at least one more connection." Accordingly, we are not
persuaded the Examiner erred.
Claim 5
Claim 5 recites "the plurality of corresponding connections that
serve the same function on both buses transmit a chip enable signal and
a clock signal as the first portion of common signals." App. Br. ("Claims
App."). (emphasis added). Appellant argues "there appears to be no
teaching in either Arnold or Chesson ( or in the Wikipedia article) that a chip
enable signal is utilized as an enable signal for a pattern-recognition
processor." App. Br. 11-12. The Wikipedia article was cited by the
Examiner in the rejection of claim 5. Final Act. 14.
We discern no error in the Examiner's reliance on the Wikipedia
article in the rejection as evidence to explain how one of ordinary skill
would have comprehended the teachings concerning DRAMs in Arnold and
Chesson. Regarding DRAM memory, the Wikipedia article, page 5, states
"[a]ll commands are timed relative to the rising edge of a clock signal," and
further states "/CS Chip Select. When this signal is high, the chip ignores
all other inputs (except for CKE), and acts as if a NOP [no-operation]
command is received." Figure 2 of Arnold shows multiple DRAM arrays
8
Appeal2017-002885
Application 12/350, 136
42, suggesting chip enable (i.e., select) signals may be used to selectively
enable them. Likewise, Chesson's Figure 6 shows DRAM Memory Banks 0
and 1, which may be selectively activated, for example, using a chip enable
signal. Hence, it appears a person of ordinary skill would have understood
to use a chip enable signal, timed relative to a clock signal, as described in
the Wikipedia article, on the buses of the DRAM chips described in Arnold
and Chesson.
Appellant's argument that the Wikipedia article does not teach a
pattern-recognition processor, and Arnold and Chesson do not teach chip
enable signals (App. Br. 12), fails to consider how one of ordinary skill
would have comprehended the combined teachings of the references and
article. In re Keller, 642 F.2d 413,425 (CCPA 1981) ("Non-obviousness
cannot be established by attacking references individually where the
rejection is based upon the teachings of a combination of references.")
Specifically, the Examiner relies on the Wikipedia article to teach the
claimed chip enable signal, and Arnold and Chesson to teach the claimed
pattern-recognition processor. As Appellant's argument does not consider
the references and article in combination as applied by the Examiner, we do
not find Appellant's argument persuasive.
Claim 8
Claim 8 recites "the portion of the pattern-recognition bus serves
the at least one different function compared to the corresponding
portion of the memory bus and the at least one different function varies
based on a mode of operation of the pattern-recognition processor."
App. Br. ("Claims App."). ( emphasis added). Appellant argues "there
appears to be no teaching in either Arnold or Chesson ( or in the Wikipedia
9
Appeal2017-002885
Application 12/350, 136
article) that different functions in a pattern-recognition processor and a
memory vary based on a mode of operation of the pattern recognition
processor, as recited in claim 8." App. Br. 12-13; Reply Br. 6.
The Examiner finds, and we agree that Arnold discloses
the address on the internal bus 68 and control words on the
internal bus 66 are passed to the monitor controller [70] [ of the
pattern monitor 12, Fig. 2, above, via the patter[n] monitor bus].
Simultaneously, the data on the internal data bus 56 is passed to
a code signature computation circuit 72 [ of the pattern monitor
12, Fig. 2 above, via the patter[n] monitor bus].
Final Act. 15 (citing Arnold 6:42--45) (with Examiner edits and panel edits
to correct typographical errors in the number "70" and the word "pattefQ").
Thus, the Examiner considers the operation of the monitor controller 70
receiving an address A and command Con internal buses 66, 68, and the
operation of the code signature computation circuit 72 receiving data D 1 on
internal bus 56 in Arnold's pattern-recognition processor, to be different
modes of operation. The Examiner also refers to the Specification which
states
Some of the signals on the pattern-recognition bus 96
may serve either the same function as on the memory bus 96 or
different functions depending on a mode of operation of the
pattern-recognition processor 14. For example, the address
signals and block address signals 136 may convey address
data when the pattern-recognition processor 14 is in a first
mode of operation, command decode signals when the
pattern-recognition processor 14 is in a second mode of
operation, and register select signals when the pattern-
recognition processor 14 is in a third mode of operation.
Ans. 38--40 (citing Spec. ,r 78) (emphasis added). However, the claim does
not recite that the pattern-recognition processor has three different modes of
10
Appeal2017-002885
Application 12/350, 136
operation in which signals on the same address lines are interpreted
differently as address, command decode, or register select signals, according
to the mode, or that the pattern-recognition processor can be in only one
mode at any particular time. Care must be exercised not to import
limitations into the claims or to read a particular embodiment appearing in
the written description into the claim if the claim language is broader than
the embodiment. In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993)
(citing In re Zletz, 893 F.2d 319,321 (Fed. Cir. 1989)).
Appellant argues that there is no pattern-recognition processor present
in the Wikipedia article, or teaching of modes of operation in Arnold or
Chesson. App. Br. 13. Again, such an argument fails to consider the
combination of the prior art. See Keller, supra. In the prior art combination,
the Examiner relied on Arnold and Chesson to teach the claimed pattern-
recognition processor, and on Arnold to teach its modes of operation. Thus,
we find Appellant's arguments unpersuasive.
Claim 45
Claim 45 recites "the pattern-recognition processor is configured
to reinterpret at least a first portion of common signals transmitted on
the memory bus and on the pattern-recognition bus to serve a different
function, wherein the pattern-recognition processor and the memory
are configured to interpret at least a second portion of the common
signals transmitted on the memory bus and on the pattern-recognition
bus to serve the same function." App. Br. ("Claims App."). (emphasis
added).
11
Appeal2017-002885
Application 12/350, 136
Appellant alleges similar arguments as already discussed for claim 1.
App. Br. 13-18; Reply Br. 7-11. We find these arguments unpersuasive for
similar reasons.
Specifically, the Examiner references the rejection of claim 1 in
connection with claim 45. Final Act. 1 7. As noted with respect to claim 1,
the Examiner found in Arnold both the memory 18 and data pattern monitor
12 perform the same functions of receiving address, command, and data on
respective internal buses 66, 68, 56, and interpreting the received signals
accordingly. Final Act. 8-9 (citing Arnold 6:31-34; see also 6:19-30, Fig.
2). We agree with the Examiner's findings, and thus Appellant's argument
is not persuasive.
Appellant also questions modification of Arnold with Chesson to
make Arnold's memory bus and pattern-recognition bus physically
independent. App. Br. 13, 16, 17. However, Appellant does not argue that
Chesson does not disclose such physically independent buses, and further
does not explain why it would be improper to modify Arnold with
Chesson's teaching of physically independent buses. Accordingly,
Appellant's argument is unpersuasive. 37 C.F.R. § 4I.37(c)(l)(iv).
Appellant further argues the "reinterpret" limitation is not taught by
Arnold and Chesson. App. Br. 13-14, 16-17. The Examiner notes that, in
Arnold, a "first portion of common signals" is the data signal on the internal
bus 56, which is interpreted by the DRAM memory 18 to serve a function of
memory data transferring associated with memory read/write operations.
Ans. 54--55 (citing 4:59---61; 5:13-30; 5:47-50; 6:21-24; 6:31-7:43, Figs. 1,
2). The Examiner also finds that Arnold's data pattern monitor 12 receives
the same data signal on internal bus 56 and reinterprets it to detect data bit
12
Appeal2017-002885
Application 12/350, 136
patterns. Id. The Examiner's interpretation is consistent with the way that
the Specification uses the word "reinterpret." Specifically, the Specification
states "[s]ome of the signals on the pattern-recognition bus 96 may be
reinterpreted from their function on the memory bus 98." Spec. ,r 77, Fig.
13. Thus, the Specification uses the word "reinterpret" to mean that the
pattern-recognition processor 14 interprets some signals to serve a different
function than does the memory 100 interpreting those same signals. As the
Examiner's interpretation is consistent with the Specification, we agree with
the Examiner's findings that Arnold teaches the "reinterpret" limitation
under a broad, but reasonable, interpretation.
Claim 7
Claim 7 recites "the memory bus is a double data rate two memory
bus." App. Br. ("Claims App.") ( emphasis added). Appellant argues the
Examiner relies on Arnold as teaching use of a DDR bus, but that Arnold
fails to disclose any DDR bus, so it would not be obvious to replace an
element not taught by Arnold with a DDR2 bus taught in the Wikipedia
article. App. Br. 18; Final Act. 17-18.
In the Answer, however, the Examiner clarifies that Arnold teaches
DRAM memory (see Arnold Fig. 2), and that the Wikipedia article teaches
DRAM memory includes DDR2 memory (see Wikipedia article, page 1).
Ans. 60. We agree with the Examiner's findings that the claimed limitation
is taught because Arnold's DRAM would have been understood by one of
ordinary skill to include DDR2 according to the Wikipedia article. Thus, we
are not persuaded by Appellant's argument.
13
Appeal2017-002885
Application 12/350, 136
Claim 12
Claim 12 recites "the pattern-recognition processor is integrated
into the same component as the PU." App. Br. ("Claims App.") (emphasis
added). Appellant contends the Examiner relied on Official Notice to render
this claim limitation obvious, and traverses the taking of Official Notice
because it is not of "a notorious character" and "capable of such instant and
unquestionable demonstration as to defy dispute." App. Br. 19-20 ( citing
M.P.E.P. § 2144.03).
In addition, Appellant contends Arnold teaches away from the
claimed invention because Arnold states its autonomous memory scrubbing
process is to be undertaken separately from operation of the CPU 14, and
one of ordinary skill thus would not have combined the references. Id. at 20
(citing Arnold 6:7-14 and 27-37). The Examiner cites Chesson's Figure 2,
shown below, as teaching the claimed feature. Ans. 63---65.
,·-·-·-----
. INSTRUCTION
60 _ __r MEMORY
24----' CPU
20
j
48
C1 .. /
fl
,.l
/ I
50 ----l
D5 I
STREAM
PROCESSING
UNITS ,,~,~,,~~,~,,,,,,,..,..,,,,,,,, '''''''' '''''''''''' ...s
(_; --.......... - ........
52
-26
MEMORY
58
.J' L__::.CO:::::.:;NTi~R;;::Ol:;::,.LE>::;:..R:..._.J__ _ ........J:!::::::::::::::i::::::.::::_::::::::..:;,;::.:::.:::.::::.:..:....::J ~-46
30 DB
55s·[Lt47A MEM~
34-5 D4
I DATA SOURCE/SINK B}"'----10
STREAM - PROCESSING ARCHITECTURE
FIG. 2
14
Appeal2017-002885
Application 12/350, 136
Specifically, in Chesson's Figure 2, the Examiner finds that the claimed
pattern-recognition processor is the pattern matcher 70 (shown in Chesson's
Fig. 3) of the stream processing units 26, and the claimed processing unit
(PU) can be interpreted as the CPU 24, the memory controller 58, or the bus
controller 44/46. Ans. 63-64. The Examiner also finds that Chesson
teaches that the devices depicted in the rectangular V numbered "20" in
Chesson's Figure 2 may be constructed as a single very-large scale
integration (VLSI) circuit. Id. (citing Chesson 4:35-37). The Examiner
further finds that claim 12 only requires that the "processing unit (PU)" and
the "pattern-recognition processor" are integrated into the same component.
Ans. 64---65. As Chesson teaches its pattern matcher 70 and CPU 24,
memory controller 58, and bus controller 44/46 are integrated in the same
VLSI circuit (Chesson 4:35-37, Fig. 2), we agree with the Examiner's
findings, and are not persuaded the Examiner erred in the rejection of claim
12.
Remaining Claims
No separate arguments are presented for the remaining claims, which
fall for the reasons stated with respect to the claims from which they depend.
37 C.F.R. § 4I.37(c)(l)(iv).
DECISION
We affirm the rejections of claims 1-13 and 45-57 under 35 U.S.C.
§ 103(a). No time period for taking any subsequent action in connection
with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
15
Appeal2017-002885
Application 12/350, 136
AFFIRMED
16