Ex Parte Pavan et al

Patent Trial and Appeal Board

Dec 17, 2012

10749130 (P.T.A.B. Dec. 17, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/749,130 12/30/2003 Alessia Pavan NUM.0104US 3296
76446 7590 12/18/2012
Trop, Pruner & Hu, P.C.
1616 S. Voss Road, Suite 750
Houston, TX 77057-2631
EXAMINER
MOVVA, AMAR
ART UNIT PAPER NUMBER
2898
MAIL DATE DELIVERY MODE
12/18/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ALESSIA PAVAN,
CESARE CLEMENTI, and LIVIO BALDI
____________

Appeal 2010-007605
Application 10/749,130
Technology Center 2800
____________

Before MARC S. HOFF, CARLA M. KRIVAK, and
ELENI MANTIS MERCADER , Administrative Patent Judges.

MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-007605
Application 10/749,130
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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 39-46. We have jurisdiction under 35 U.S.C. § 6(b).
We Affirm.

THE INVENTION
Appellants’ claimed invention is directed to a dielectric layer 9 having
a low dielectric constant formed between floating gate regions FG belonging
to the same memory cell matrix row in order to reduce coupling between
adjacent cells 1. (See Spec. ¶ [37] and Fig. 9).
Independent claim 39, reproduced below, is representative of the
subject matter on appeal.
39. A memory comprising:
a pair of adjacent cells having separate floating gates;
a field oxide between said cells;
a first dielectric covering said floating gates and said field oxide;
a second dielectric over said first dielectric between said floating
gates, said
second dielectric having a lower dielectric constant than said first
dielectric; and
a control gate over said first and second dielectrics.

REFERENCES and REJECTIONS
1. The Examiner rejected claims 39 and 41-43 under 35 U.S.C.
§102(b) as being anticipated by Arai (US Patent 6,329,688 B1).
2. The Examiner rejected claims 39, 41, and 46 under 35 U.S.C.
§102(b) as being anticipated by Tanimoto (US Patent Application
2002/0025630).
Appeal 2010-007605
Application 10/749,130
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3. The Examiner rejected claims 40 and 44 under 35 U.S.C. § 103(a)
as unpatentable over Arai in view of Liu (US Patent 5,923,063).
4. The Examiner rejected claims 40 and 44 under 35 U.S.C. § 103(a)
as unpatentable over Arai in view of Ahn (US Patent Application
2001/0038132).

ISSUE
The issue is whether the Examiner erred in finding that Arai teaches
the limitation of: “a second dielectric over said first dielectric between said
floating gates” as recited in claim 39.

PRINCIPLES OF LAW
“[O]ne cannot show non-obviousness by attacking references
individually where . . . the rejections are based on combinations of
references.” In re Keller, 642 F.2d 413, 426 (CCPA 1981).

ANALYSIS
Claims 39 and 41-43
Appellants argue that claim 39 requires the second dielectric be over
the first dielectric between the floating gates (Br. 10). Appellants
specifically argue that because Arai’s layer 5c stops exactly at the edge of
the floating gate 4 (see Arai’s Fig. 2) then the Examiner’s interpretation of
“a first dielectric layer” as required by claim 39 fails (Br. 10). Appellants
also allege that the Examiner’s interpretation of “first dielectric layer” as
recited in claim 39 does not satisfy claim 42, which requires that the first
dielectric layer include oxide/nitride/oxide because only layers 5a (i.e.,
oxide) and 5b (i.e., nitride) are between the floating gates 4 (see Br. 10).
Appeal 2010-007605
Application 10/749,130
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We do not agree with Appellants’ argument. Appellants’ argument is
not commensurate in scope with claim 39. Claim 39 requires that the second
dielectric layer be over the first dielectric layer and between the floating
gates (see claim 39). Thus, we agree with the Examiner that the disputed
limitation of claim 39 is met by the second dielectric layer 10 being over the
first dielectric layer 5 (i.e., including layers 5a, 5b, and 5c) and between the
floating gates 4 (see Fig. 2 and Ans. 3). Nothing in the claim language
requires layer 5 (5a, 5b, and 5c) be between the floating gates.
Claim 42 is met by Arai’s teaching that layer 5 (i.e., first dielectric
layer) includes ONO (i.e., silicon oxide film 5a, silicon nitride film 5b, and
silicon oxide film 5c) (col. 8, ll. 59-63).
Accordingly, we affirm the Examiner’s rejection of claims 39 and 42.
For the same reasons we also affirm the Examiner’s rejection of claims 41
and 43 which were not separately argued (Br. 10).
Claims 40 and 44-46
Appellants do not make any additional arguments of patentability with
respect to claims 40 and 44-46. Accordingly, we pro forma affirm the
Examiner’s rejections of these claims.

CONCLUSION
The Examiner did not err in finding that Arai teaches the limitation of
“a second dielectric over said first dielectric between said floating gates” as
recited in claim 39.

DECISION
The Examiner’s decision rejecting claims 39-46 is affirmed.
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Application 10/749,130
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010).

AFFIRMED

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