Ex Parte Patariu et al

Board of Patent Appeals and Interferences

May 30, 2012

10417051 (B.P.A.I. May. 30, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/417,051 04/16/2003 Kevin Patariu 3875.0070000 5953
26111 7590 05/31/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
GEE, JASON KAI YIN
ART UNIT PAPER NUMBER
2434
MAIL DATE DELIVERY MODE
05/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
________________

Ex parte KEVIN PATARIU, IUE-SHUENN CHEN, JAY KWOK WA LI,
CYNTHIA DANG, and MARK TAYLOR CORE

________________

Appeal 2010-000650
Application 10/417,051
Technology Center 2400
________________

Before KALYAN K. DESHPANDE, JASON V. MORGAN, and
ERIC B. CHEN, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
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STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1 – 3, 5 – 9, and 11 – 15, and 17 – 28. The Examiner
finds that claims 4, 10, and 16 would be allowable if rewritten in
independent form (Ans. 2). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Invention
The invention relates to a method and system for secure access and
processing of an encryption/decryption key (see Spec. ¶ [0004]). Secure
access and processing is provided by generating keys within a key controller
block of a chip and transferring the generated keys to an on-chip bus
interface (see Abstract).
Exemplary Claim
1. A method for secure encryption and decryption key
processing, the method comprising:
generating at least one key within a key controller block of a
chip;
transferring within said chip, said generated at least one key
from said key controller block of said chip to an on-chip bus
interface block via a secure serial link, wherein said generated
at least one key is transferred utilizing a serial data signal;
validating said transferred at least one key using a serial data
validation signal, wherein said serial data validation signal is
generated within said chip; and
storing said validated at least one key in at least one register
which is accessible by only said key controller block.
(Emphases added).
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Evidence and Rejection
The Examiner rejects claims 1 – 3, 7 – 9, 13 – 15, and 19 under 35
U.S.C. § 103(a) as being unpatentable over Oishi (US 2001/0052070 A1),
Hamilton (US 5,016,277), Tripathy (US 7,110,542 B1), and Trimberger (US
7,200,235 B1) (Ans. 4 – 7).
The Examiner rejects claims 5, 11, and 17 under 35 U.S.C. § 103(a) as
being unpatentable over Oishi, Hamilton, Tripathy, Trimberger, and Matyas
(US 4,206,315) (Ans. 7 – 8).
The Examiner rejects claims 6, 12, 18, 21, 22, 24, 25, 27, and 28
under 35 U.S.C. § 103(a) as being unpatentable over Oishi, Hamilton,
Tripathy, Trimberger, Matyas, and Rodriguez (US 2002/0059623 A1) (Ans.
8 – 9).
ISSUES
1. Did the Examiner err in finding that the combination of Oishi and
Tripathy teaches or suggests transferring within a chip a generated key from
a key controller block of the chip to an on-chip bus interface block, as
recited in claim 1?
2. Did the Examiner err in finding that the combination of Oishi and
Trimberger teaches or suggests validating the transferred key using a serial
data validation signal, wherein the serial data validation signal is generated
within the chip, as recited in claim 1?
3. Did the Examiner err in finding that the combination of Oishi,
Tripathy, and Rodriguez teaches or suggests wherein the on-chip bus
interface block is an integrated drive electronics (IDE) bus interface, as
recited in claim 6?
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ANALYSIS
Claims 1 – 3, 5, 7 – 9, 11, 13 – 15, 17, 19, 20, 23, and 26
The Examiner rejects claim 1, finding, for example, that Oishi teaches
generating a key within a key controller block on a chip, and transferring the
key another on-chip block via a secure link (Ans. 4 – 5 (citing Oishi
¶¶ [0019], [0045], and [0057]). Further, the Examiner relies on Tripathy to
teach or suggest that the destination block can be a bus interface block
(Ans.5 (citing Tripathy, col. 5, ll. 1 – 10)) and relies on Trimberger to teach
or suggest the use of a serial data validation signal (Ans. 6 (citing, e.g.,
Trimberger, col. 3, ll. 20 – 35)).
Appellants argue that while Oishi discloses transferring a key to an
encryption unit 30, this unit only functions to execute encryption and
decoding using an encryption key; the unit does not interface with a bus (see
App. Br. 14). Appellants argue that Tripathy does not cure this deficiency
because Tripathy’s bus interface unit 160 is distinct and separate from the
encryption/decryption unit 150 (see App. Br. 16). However, these arguments
are tantamount to Appellants attacking the references individually and
Appellants cannot show error in the Examiner’s rejection, which is based on
the combined teachings and suggestions of Oishi and Tripathy, by attacking
each reference individually. See In re Keller, 642 F.2d 413, 426 (CCPA
1981).
Here, the Examiner has shown that the combination of Oishi and
Tripathy teaches or suggests transferring a generated key from a key
controller to an on-chip block (as taught by Oishi), where the block can be a
bus interface (as taught by Trimberger) (see Ans. 4 – 5 and 9 – 11).
Furthermore, Oishi teaches an on-chip block (lower-layer interface unit 10)
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that can establish a connection to a serial bus (Oishi, ¶ [0039]). Tripathy
teaches that multi-function chip 196, which has the encryption/decryption
unit 150, can provide many additional features (Tripathy, col. 9, ll. 13 – 14),
which an artisan of ordinary skill would realize could include the features of
the bus interface unit coupled to the multi-function chip 196 (Tripathy, col.
9, ll. 12 – 13). Thus, contrary to Appellants’ assertions, both Oishi and
Tripathy teach or suggest an on-chip bus interface block.
Appellants further contend that the Examiner erred in finding that the
combination of Oishi and Trimberger teaches or suggests the validating step
of claim 1 because Trimberger’s “CRC value, although generated by an
on-chip CRC generator, is nevertheless initiated from an external input
to the FPGA 31 by the user for verifying the user decryption key” (App.
Br. 19) (emphases in the original). However, claim 1 is silent as to how
generation of the serial data validation signal is initiated. Appellants’
argument is not commensurate with the scope of the claimed invention and,
therefore, not persuasive of error in the rejection.
Accordingly, we sustain the rejection of claim 1, as well as the
rejections of claims 2, 3, 5, 7 – 9, 11, 13 – 15, 17, 19, 20, 23, and 26, which
are not argued separately (see App. Br. 20 – 22).1
Claims 6, 12, 18, 21, 22, 24, 25, 27, and 28
The Examiner finds that Rodriguez shows that IDE bus interfaces
storing information is well known in the art (see Ans. 8 (citing Rodriguez

1 Appellants do not argue claims 5, 11, and 17 separately with specificity
because the arguments Appellants make are based on recitations found in
claims 4, 10, and 16, but not in claims 5, 11, and 17 (see App. Br. 20 – 22).
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¶ [0028])). Appellants argue that the bus interface in Rodriguez is between
two systems, a digital home communication terminal and a storage system,
“where neither of the two systems is within a chip” (emphases in the
original). (App. Br. 23). However, as discussed supra, the combination of
Oishi and Tripathy teaches or suggests an on-chip bus interface. The
Examiner correctly further relies on Rodriguez to teach or suggest that a bus
interface can be an IDE bus interface (see Ans. 8).
Appellants further argue that Tripathy’s peripheral component
interconnect bus interface 160 teaches away from an on-chip interface bus
(Reply Br. 8). However, Appellants do not show evidence that Tripathy
criticizes, discredits, or otherwise discourages the alternative of an on-chip
bus interface. See In re Fulton, 391 F.3d 1195, 1200 – 1201 (Fed. Cir. 2004).
Therefore, Appellants do not show that Tripathy discourages or leads an
artisan of ordinary skill away from an on-chip IDE bus interface block. See
In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994).
Accordingly, we sustain the rejection of claim 6, as well as the
rejection of claims 12, 18, 21, 22, 24, 25, 27, and 28, which are not argued
separately (see App. Br. 24).
DECISION
We affirm the Examiner’s decision to reject claims 1 – 3, 5 – 9, and
11 – 15, and 17 – 28.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED
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