Ex Parte Pasadyn et al

Board of Patent Appeals and Interferences

Aug 25, 2009

10156541 (B.P.A.I. Aug. 25, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ALEXANDER J. PASADYN, and CHRISTOPHER A. BODE
____________

Appeal 2008-005430
Application 10/156,541
Technology Center 2100
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Decided: August 25, 2009
____________

Before ALLEN R. MACDONALD, Vice Chief Administrative Patent Judge,
ST. JOHN COURTENAY III, and
DEBRA K. STEPHENS Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-36, which are all of the claims remaining in this
application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
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The Invention
Appellants’ invention relates to semiconductor manufacturing. More
particularly, the invention on appeal relates to modeling inline parameters
and end-of-line (EOL) parameters for controlling processing of
semiconductor wafers based upon the EOL parameters. (Spec. 1, ll. 6-9).
Claim 1 is illustrative:
1. A method, comprising:

determining a target end-of-line parameter relating to a semiconductor
wafer by modeling said end-of-line parameter; and

controlling an inline parameter relating to processing of said
semiconductor wafer in response to said target end-of-line (EOL) parameter
using a controller, controlling said inline parameter comprising adjusting a
target inline parameter that correlates to said EOL parameter.

Prior Art
The Examiner relies on the following references as evidence:
Simmons US 6,613,590 B2 Sep. 2, 2003
Shanmugasundram US 2003/0199112 A1 Oct. 23, 2003

Examiner’s Rejections
1. The Examiner rejected claims 1-7, 9-32, and 34-36 under
35 U.S.C. § 102(e) as being anticipated by Shanmugasundram.
2. The Examiner rejected claims 8 and 33 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Shanmugasundram
and Simmons.

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FINDINGS OF FACT
In our analysis infra, we rely on the following findings of fact (FF):
1. Shanmugasundram discloses collecting wafer properties in real-
time during processing or immediately after processing. The properties may
be forwarded back to the instant functional units to optimize processing
operations. (Para. [0039]).
2. Shanmugasundram discloses that incoming wafer properties
may be transferred for use in optimizing processing. The properties may be
inputted into functional unit models. (Para. [0040]).
3. Shanmugasundram discloses that the functional unit models
generate or modify the recipe that leads to optimal outputs or results. (Id.).
4. Shanmugasundram discloses that “recipes constitute a set of
predefined process parameters believed to be required to effectuate a
functional unit processing outcome . . . [t]hus, a recipe may identify the
required temperature, pressure, power, processing time, lift position, and
flow rate of a material needed to produce a particular target wafer result.”
(Para. [0036]).
5. Shanmugasundram discloses that “[e]xamples of these [target
wafer] results include film thickness, uniformity profiles, via depth, trench
depth, sheet resistance, uniformity of the copper patterns, etc.” (Para.
[0036]).
6. Shanmugasundram discloses that recipes are generated by
models (Para. [0036]).

7. Appellants disclose specific examples of end-of-line parameters
associated with devices, as follows:
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Embodiments of the present invention provide for
associating targeted end-of-line parameters with
particular inline parameters, such that adjustments
to the inline parameters may be made to achieve
the targeted end-of-line (EOL) parameters. The
end-of-line parameters may include, but are not
limited to, the yield relating to devices produced
from the processed semiconductor wafers 105, the
reliability of such devices, the performance of such
devices, and the like.
(Spec. 9, ll. 1-7).
8. Appellants disclose specific examples of inline parameters
associated with wafers, as follows:

The inline parameters may include, but are not
limited to, one of many measured factors of a
processed semiconductor wafer 105, such as the
critical dimensions of one or more structures
formed on the semiconductor wafers 105, the film
thickness resulting from a particular process
performed on the semiconductor wafers 105, the
accuracy of the overlay after photolithography
processes, electrical resistivity measurements
between at least two points on a semiconductor
wafer 105, a duration of a deposition process, and
the like.
(Spec. 9, ll. 7-13).

APPELLANTS’ CONTENTION
Appellants contend that Shanmugasundram fails to disclose the
limitation of “determining a target end-of-line parameter relating to a
semiconductor wafer by modeling said end-of-line parameter,” as claimed.
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(App. Br, 9-10; Reply Br. 2-3). We note that this limitation is recited in
commensurate form in each independent claim on appeal. (Independent
claims 1, 12, 17, 18, 22, and 26).

ISSUE
Based upon our review of the administrative record, we have
determined that the following issue is dispositive in this appeal:
Have Appellants shown the Examiner erred in determining that
Shanmugasundram discloses “determining a target end-of-line parameter
relating to a semiconductor wafer by modeling said end-of-line parameter?”
(Independent claims 1, 12, 17, 18, 22, and 26).

PRINCIPLES OF LAW
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006). Therefore, we look to Appellants’ Briefs to show error in
the Examiner’s proffered prima facie case.
Anticipation
“Anticipation requires the presence in a single prior art reference
disclosure of each and every element of the claimed invention, arranged as
in the claim.” Lindemann Maschinenfabrik GmbH v. American Hoist &
Derrick Co., 730 F.2d 1452, 1458 (Fed. Cir. 1984).

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ANALYSIS
Anticipation Rejection of claims 1-7, 9-32, and 34-36
We decide the question of whether Shanmugasundram discloses
“determining a target end-of-line parameter relating to a semiconductor
wafer by modeling said end-of-line parameter.” Based upon our review of
the record, as discussed infra, we find the weight of the evidence supports
the Appellants’ position.
Claim Construction
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re Amer. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364
(Fed. Cir. 2004) (citations omitted). We begin our analysis by broadly but
reasonably construing the recited terms “end-of-line parameter” and “inline
parameter.” When we look to Appellants Specification for context, we note
that “end-of-line parameters” are described as follows:
end-of-line parameters may include, but are not
limited to, the yield relating to devices produced
from the processed semiconductor wafers 105, the
reliability of such devices, the performance of such
devices, and the like.
(FF 7).
Appellants describe “inline parameters” as follows:

The inline parameters may include, but are not
limited to, one of many measured factors of a
processed semiconductor wafer 105, such as the
critical dimensions of one or more structures
formed on the semiconductor wafers 105, the film
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thickness resulting from a particular process
performed on the semiconductor wafers 105, the
accuracy of the overlay after photolithography
processes, electrical resistivity measurements
between at least two points on a semiconductor
wafer 105, a duration of a deposition process, and
the like.
(FF 8).

Consistent with Appellants’ Specification, we broadly but reasonably
construe the claim term “end-of-line parameter” as a parameter associated
only with already-manufactured semiconductor devices (e.g., yield,
reliability, and performance). (FF 7).
Consistent with Appellants’ Specification, we broadly but reasonably
construe the recited “inline parameter” as a parameter associated only with
measured factors of a processed semiconductor wafer (e.g., critical
dimensions, film thickness, and electrical resistivity between points on the
wafer). (FF 8).
The Examiner relied on Paragraphs [0039]-[0040] of
Shanmugasundram to teach the aforementioned limitation. (See Ans. 3-4
and 10-11). In particular, the Examiner points to Shanmugasundram’s
desired target wafer results (e.g., film thickness, uniformity profiles, sheet
resistance, etc.) as corresponding to the recited end-of-line parameters where
Shanmugasundram’s end-of-line parameters are purportedly the result of
recipes that are controlled by models. (Ans. 10-11; see also FF 5).
However, consistent with our aforementioned claim construction, we
find parameters associated with the measured factors of a processed
semiconductor wafer (such as critical dimensions, film thickness, and
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electrical resistivity) correspond to the claimed inline parameter. Such
exemplary inline parameters are distinguished from the claimed end-of-line
parameter that is associated only with already-manufactured semiconductor
devices (e.g., yield, reliability, and performance). Our interpretation is fully
consistent with Appellants’ Specification, as discussed supra.
In particular, we observe that the Examiner is reading the recited end-
of-line parameter on one or more specific parameters in the
Shanmugasundram reference (film thickness and resistance) that are clearly
described in Appellants’ Specification as corresponding to inline
parameters. (FF 8). Thus, we find the Examiner has construed the claim
term end-of-line parameter in a manner that is inconsistent with Appellants’
Specification. (FF 7-8).
We find that Shanmugasundram’s “recipes” are a set of inline
parameters, i.e., measured factors of a processed semiconductor wafer. (FF
1-4). Specifically, Shanmugasundram discloses that “recipes constitute a set
of predefined process parameters believed to be required to effectuate a
functional unit processing outcome . . . [t]hus, a recipe may identify the
required temperature, pressure, power, processing time, lift position, and
flow rate of a material needed to produce a particular target wafer result.”
(FF 4).
Regarding the claimed modeling of an end-of-line parameter, we find
Shanmugasundram discloses that the recipes (that identify required inline
parameters to produce target wafer results) are generated by models, and not
that end-of-line parameters themselves are modeled, as required by the
express language of the claim (FF 6). Consistent with our aforementioned
claim construction, parameters associated with measured factors of a
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processed semiconductor wafer are inline parameters, and are clearly
distinguished from end-of-line parameters that are associated with finished
semiconductor devices. Therefore, we find the Examiner, has not
demonstrated how the claimed end-of-line parameters are modeled by
Shanmugasundram.
Accordingly, we agree with Appellants’ contention that “the operation
and processes required to obtain the final products disclosed
Shanmugasundram merely refer to performing operations and processes to
produce a final wafer product, not for any modeled target end-of-line
parameter [i.e., associated only with an already-manufactured semiconductor
device], as called for by [independent] claims 1, 12, 17, 18, 22, and 26 of the
present invention.” (App. Br. 21, emphasis in original).
We note that “absence from the reference of any claimed element
negates anticipation.” Kloster Speedsteel AB v. Crucible, Inc., 793 F.2d
1565, 1571 (Fed. Cir. 1986).
Based on the record before us, we agree that Appellants’ have shown
the Examiner erred in rejecting independent claims 1, 12, 17, 18, 22, and 26
as being anticipated by Shanmugasundram for essentially the same reasons
argued by Appellants, as discussed above. Accordingly, we reverse the
Examiner’s anticipation rejection of each independent claim on appeal as
well as the Examiner’s anticipation rejection of associated dependent claims
2-7, 9-11, 13-16, 19-21, 23-25, 27-32 and 34-36.

Obviousness Rejection of Claims 8 and 33
We consider next the Examiner’s rejection of dependent claims 8 and
33 as being unpatentable over the combination of Shanmugasundram and
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Simmons. We do not find, nor has the Examiner established, that Simmons
cures the deficiencies of Shanmugasundram discussed supra. Accordingly,
we reverse the Examiner’s § 103 rejection of claims 8 and 33.

CONCLUSION
Appellants have shown the Examiner erred in determining that
Shanmugasundram discloses “determining a target end-of-line parameter
relating to a semiconductor wafer by modeling said end-of-line parameter.”

DECISION
The Examiner’s decision rejecting claims 1-7, 9-32, and 34-36 under
35 U.S.C. §102(e) is reversed.
The Examiner’s decision rejecting claims 8 and 33 under 35 U.S.C.
§103(a) is reversed.

REVERSED

pgc

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