11604678 (P.T.A.B. Dec. 20, 2012)

Ex Parte Park et al

Patent Trial and Appeal BoardDec 20, 2012

11604678 (P.T.A.B. Dec. 20, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/604,678 11/28/2006 Chang-Yong Park 9862-000053/US/01A 4028 30593 7590 12/20/2012 HARNESS, DICKEY & PIERCE, P.L.C. P.O. BOX 8910 RESTON, VA 20195 EXAMINER RODELA, EDUARDO A ART UNIT PAPER NUMBER 2893 MAIL DATE DELIVERY MODE 12/20/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte CHANG-YONG PARK, BYUNG-MAN KIM, DONG-CHUN LEE, YONG-HYUN KIM, KWANG-SEOP KIM, DONG-WOO SHIN, and KWANG-HO CHUN ____________ Appeal 2010-005561 Application 11/604,6781 Technology Center 2800 ____________ Before DENISE M. POTHIER, JEFFREY S. SMITH, and JOHN A. EVANS, Administrative Patent Judges. EVANS, Administrative Patent Judge DECISION ON APPEAL This is an appeal under 35 U.S.C. § 134(a) involving claims to semiconductor modules. The Examiner has rejected the claims as obvious. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Rather than reiterate the arguments of Appellants and the Examiner, 1 The real party in interest is Samsung Electronics Co., Ltd. Appeal 2010-005561 Application 11/604,678 2 we refer to the Appeal Brief (filed June 10, 2009), the Examiner’s Answer (mailed October 6, 2009), and the Reply Brief (filed December 7, 2009). We have considered in this decision only those arguments Appellants actually raised in the Briefs. Any other arguments which Appellants could have made but chose not to make in the Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(iv). STATEMENT OF THE CASE The claims relate to a semiconductor module including at least one semiconductor chip package and a board having functional pads and dummy pads and, at least one supporting solder bump is formed on one of the dummy pads. Claims 1-11 are on appeal. The rejection of claims 12-21 has been withdrawn. Ans. 2. An understanding of the invention can be derived from a reading of Claim 1, the sole independent claim on appeal, which is reproduced below with disputed limitations italicized with some paragraphing added: 1. A semiconductor module, comprising: at least one semiconductor chip package; a board having functional pads and dummy pads; at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board; and at least one supporting solder bump formed on one of the Appeal 2010-005561 Application 11/604,678 3 dummy pads and disposed under a portion of the semiconductor chip package, the supporting solder bump having an arcuate surface that faces the semiconductor chip package. Claims 1-11 stand rejected under 35 U.S.C. § 103(a) as obvious over Ichihara (US 6,727,718 B2; issued Apr. 27, 2004, filed November 19, 2002) and Kimura (US 2003/0060035 A1; issued March 27, 2003). (Ans. 3-6).2 Appellants’ Appeal Brief argues claims 1-10 as a group and separately argues claim 11. We decide the appeal on that basis. See 37 C.F.R. 41.37(c)(1)(vii). CLAIMS 1-10 CONTENTIONS AND ISSUE The Examiner finds that Ichihara teaches every element of claim 1, except that Ichihara does not teach wherein the supporting solder bump faces the semiconductor chip package. The Examiner finds that Kimura shows in Figure 10 the supporting solder bump [8] faces the semiconductor chip package [1]. (Ans. 3-4). Appellants contend the claims recite that at least one supporting solder bump is formed on one of the dummy pads of the board. Appellants contend that Ichihara discloses that the reinforcing solder bumps [15] are formed on footprints [14] in an area of the package body [11], but are not formed on one of the functional dummy pads of the board, as claimed. (See App. Br. 2 Seyama, US 6,693,362 B2, filed November 20, 2001, is additionally cited when rejecting claim 11 as supporting a proposition the Examiner finds to be well-known in the art. See Ans. 6, 8. Thus, claim 11 has been rejected based on Ichihara, Kimura, and Seyama. Appeal 2010-005561 Application 11/604,678 4 13-14). Appellants further contend that Kimura shows dummy bumps [3] formed on the chip [1], but not formed on the board. Appellants contend that claim 1 recites “the supporting solder bump having an arcuate surface that faces the semiconductor chip package,” but that this limitation is not taught by the cited art. Appellants contend that the Examiner finds that supporting solder bump [15] of Ichihara “has an arcuate surface that is convex with respect to the board [20].” (App. Br. 14)(citing Final Action, 2). Appellants contend that Figure 11 of Ichihara shows bump [15] has an arcuate surface that does not face the semiconductor chip package, as claimed. (App. Br. 15). Appellants further contend that the Examiner admits that Ichihara does not teach the supporting solder bump faces the semiconductor package. (App. Br. 15)(citing Final Action 3). Appellants contend that Kimura does not cure this alleged deficiency of Ichihara. Appellants contend that Kimura shows dummy bumps [3], but that they are formed on the chip [1] and their arcuate surface faces the mounting member/substrate. (App. Br. 16)(citing Kimura paragraph [0032]). Appellants contend that resilient projections [8] of Kimura are not dummy solder bumps so, therefore, are not relevant to the claims. (App. Br. 16). The issue with respect to this rejection is whether the placement of dummy bumps on a circuit board and facing an opposed semiconductor chip package is rendered obvious by the cited art. App App that (circ that form Ans. dum chip show Kim show Kim eal 2010-0 lication 11 Appellan they are fo uit board) Kimura sh ed on the 3-4). We my bumps mounting n as havin ura paragr s dummy ura, paragr Kimura Figu 05561 /604,678 ts conced rmed on th facing the ows in Fig circuit boa agree with (“resilien member 4 g an arcua aph 0031; bump 8 is aph 0034) re 10 show A e that Ichih e chip and chip. (See ure 10 wh rd facing t the Exam t projectio . (See Kim te surface see also A formed on . ing dummy 5 NALYSIS ara show not on th App. Br. erein the s he semico iner. Kimu ns 8”) may ura, parag facing sem ns. 7). Th an insula bumps form s dummy b e mountin 13-14). T upporting nductor ch ra’s figur be provid raph 0040 iconduct e below Fi ting protec ed on a chip umps, but g member he Examin solder bum ip packag e 10 show ed on a su ). Dummy or chip 1. gure 10 fu tive film mounting m contend /substrate er finds ps are e. (See s that rface of a bump 8 i (See rther 6. (See ember. s Appeal 2010-005561 Application 11/604,678 6 This insulating film 6 acts similar to the footprints 23 and 12 in Ichirhara that the Examiner mapped to the dummy pads. See Ans. 3, 7. Thus, the above discussion of Kimura and Ichihara illustrate, contrary to Appellants’ assertions (App. Br. 13-14, 16), that a supporting bump is located and formed on one of the dummy pads of a board and its arcuate surface faces the chip package. Appellants contend that the bumps of Kimura Figure 10 are formed of a resilient material, but not solder and, therefore, are not relevant to the claims. (See App. Br. 14, 16). We find Appellants’ argument to be unpersuasive. Kimura teaches that “resilient projections” are equivalent to “dummy bumps.” (Kimura [0039]) and that one skilled in the art would have recognized them as interchangeable. Additionally, such a modification of Ichihara based on Kimura’ teaching such that the bump’s arcuate surface faces the semiconductor chip package is merely a combination of familiar elements according to known methods that does no more than yield predictable results – an obvious improvement, see KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), that can be implemented by a person of ordinary skill, id. at 417. In view of the foregoing, we sustain the rejection of claims 1-10. CLAIM 11 CONTENTIONS AND ISSUE With respect to claim 11, the Examiner makes similar findings as for claims 1-10 as discussed above. However, the Examiner finds that Ichihara Appeal 2010-005561 Application 11/604,678 7 does not show where a back side of a board has dummy and functional pads and associated chip and solder joints. The Examiner finds that it is conventional in the art to place a first chip on a top side of a circuit board and a second chip on a bottom side of a circuit board. In evidence of this proposition, the Examiner cites Seyama Figure 15. (See Ans. 6). Appellants re-allege their arguments discussed above, that we find not persuasive. (App. Br. 17). Appellants further contend that ordinal 110 of Seyama in Figure 15 is a thin film and not a circuit board, as found by the Examiner. (App. Br. 17). We find that Seyama describe their thin film 110 as a flexible circuit board: FIG. 7A to FIG. 7C show the thin film 110. As shown in FIG. 7A, the thin film 110 comprises an insulating layer 113 made of polyimide, a power-supply layer 114 made of Cu, an insulating layer 115 made of polyimide, a ground layer 116 made of Cu, an insulating layer 117 made of polyimide, a signal layer 118 made of Cu, and an insulating layer 119 made of polyimide, in this order from the under surface 112. The thin film also comprises a plurality of via holes 120, a plurality of electrode pads 121 on the upper surface 111, and a plurality of electrode pads 122 on the under surface 112. The thin film 110 does not have a core material, and thus is flexible. (Seyama, col. 6, ll. 40-51). The multichip module 50B comprises the LSI chip 60 and the chip capacitors 70 and 72 as bypass capacitors mounted on the upper surface of the thin film 110, and the LSI chip 61 and the chip capacitors 71A and 73A as bypass capacitors mounted on the under surface of the thin film 110. (Seyama, col. 10, ll. 34-39). Appeal 2010-005561 Application 11/604,678 8 Seyama describe their thin film 110 as substantially-flat structure having a plurality of electrically-conductive copper layers interleaved with, and sandwiched between, insulating layers. The copper layers are patterned into power-supply, ground, and signal layers. A person of skill in the art would recognize Seyama to have disclosed a circuit board.3 In view of the teachings of Seyama, we do not find Appellants’ arguments persuasive. We, therefore, affirm the rejection of claim 11. SUMMARY We affirm the rejection of claims 1-11 as obvious. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED rwk 3 Circuit board n. A flat piece of insulating material…on which electrical components are mounted and interconnected to form a circuit. Most modern circuit boards use patterns of copper foil to interconnect the components. The foil layers may be on one or both sides of the board, and, in more advanced designs, in several layers within the board. Microsoft® Computer Dictionary, 99 (5th ed. 2002).