Ex Parte Park et al

Patent Trial and Appeal Board

Nov 14, 2013

11224313 (P.T.A.B. Nov. 14, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/224,313 09/13/2005 Wan-jun Park 2557SI-000339/US 8747
30593 7590 11/14/2013
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON, VA 20195
EXAMINER
FOURSON III, GEORGE R
ART UNIT PAPER NUMBER
2823
MAIL DATE DELIVERY MODE
11/14/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte WAN-JUN PARK,
BYOUNG-HO CHEONG,
EUN-JU BAE, HANS KOSINA,
and MAHDI FOURFATH
____________

Appeal 2011-008433
Application 11/224,313
Technology Center 2800
____________

Before BRADLEY R. GARRIS, PETER F. KRATZ, and MARK
NAGUMO, Administrative Patent Judges.

GARRIS, Administrative Patent Judge.

DECISION ON APPEAL

Appellants appeal under 35 U.S.C. § 134 from the Examiner's
decision rejecting claims 1-19. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.
Appellants claim a transistor comprising a substrate 40, insulating
layer 42, first and second metal layers 46, 48, a nanotube channel 44,
insulating layer 50, and at least two gate electrodes 52, 54, "each of the at
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Application 11/224,313

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least two gate electrodes covering top surfaces and side surfaces of only one
of the first and second metal layers" (claim 1, Fig. 3). Appellants also claim
a method of manufacturing such a transistor (claims 10 and 19).
A copy of representative independent claim 1, taken from the Claims
Appendix of the Appeal Brief, appears below.
1. A transistor comprising:
a substrate;
a first insulating layer formed on the substrate:
first and second metal layers formed on the first insulating layer and
spaced apart from each other;
a nanotube channel formed on the first insulating layer, the first and
second metal layers overlapping the nanotube channel;
a second insulating layer covering the nanotube channel; and
at least two gate electrodes formed on the second insulating layer, the
at least two gate electrodes being electrically insulated from each other and
each of the at least two gate electrodes covering top surfaces and side
surfaces of only one of the first and second metal layers.

Under 35 U.S.C. § 103(a), the Examiner rejects independent claims 1,
10, and 19 as unpatentable over Dai et al. (US 2004/0144972 A1, pub. Jul.
29, 2004 (hereafter Dai)) in combination with Nihey (US 2004/0238887 A1,
pub. Dec. 2, 2004) and Zhang et al. (US 2004/0036128 A1, pub. Feb. 26,
2004 (hereafter Zhang)) and rejects the remaining dependent claims on
appeal as unpatentable over these references alone or in combination with
additional prior art.
Appellants' arguments are directed to the above quoted claim 1
limitation which is common to each of the independent claims (Br. 13-18).
No arguments are specifically directed to the dependent claims on appeal
(id.). Therefore, in our assessment of this appeal, we have focused on
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representative independent claim 1 with which all other claims 2-19 will
stand or fall.
We will sustain the above rejections based on the findings of fact,
conclusions of law, and rebuttals to arguments which are well expressed by
the Examiner in the Answer. The comments below are added for emphasis.
The Examiner finds that the two gate electrodes of Dai's transistor do
not cover the top and side surfaces of the metal source/drain layers as
required by independent claim 1 (Ans. 3-4). Concerning this deficiency, the
Examiner finds that Zhang discloses transistors having gate electrodes which
overlap source/drain conductors as shown, for example, in Figure 1 (id. at
4). The Examiner recognizes that the gate electrodes shown, for example, in
Figure 1 of Zhang are pi-gates (id.) rather than gate electrodes of the type
taught by Dai but finds that Zhang discloses using gates other than pi-gates
such as double gates, vertical double gates, planar multi-gates and vertical
triple gates (id. at sentence bridging 4-5 citing Zhang para. 47). The
Examiner finds that Zhang's disclosure of using other gates such as double
gates and planar multi-gates encompasses plural gates of the type used by
Dai (id. at 5).
In light of these findings, the Examiner concludes that it would have
been obvious to form the gate electrodes of Dai such that they overlap (i.e.,
cover the top and side surfaces of) Dai's source/drain conductors in
accordance with the teachings of Zhang (id.).
Appellants concede that Zhang discloses using gates other than pi-
gates but argues "this one generic sentence fails to provide the requisite
teaching and motivation sought by the Examiner" (Br. 16). According to
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Appellants, "it is not even clear what arrangement is intended by Zhang’s
cursory reference to the '[o]ther types of gates' including 'double gates,'
'triple gates,' and 'quadruple gates,' [citing Zhang para. 47]" (id.).
Appellants' argument lacks convincing merit. We agree with the
Examiner that Zhang's disclosure of other gates would have been understood
by one having ordinary skill in this art as including the plural gates disclosed
by Dai in Fig. 4c to enable a logical OR gate (Ans. 6; cf., Br. 16). More
specifically, we agree with the Examiner's finding that the plain meanings of
the terms used by Zhang in describing these other gates encompass multiple
local gate electrodes of the type taught by Dai (id. at 7). It is appropriate to
emphasize that Appellants do not contest this latter finding (i.e., no Reply
Brief has been filed).
On this record, Appellants unsubstantiated arguments do not identify
reversible error in the Examiner’s determinations that one of ordinary skill in
the art would have found the overlapping arrangement of the gate electrodes
with respect to the source/drain conductors as depicted in Figure 1 of Zhang
(with pi-gates) as being applicable to the formation of the other types of
gates disclosed by Zhang and, correspondingly, that one of ordinary skill in
the art would have been led to employ such an overlapping gate arrangement
as an obvious alternative for arranging the plural gates of Dai (id. 6-7).
The decision of the Examiner is affirmed.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
cam