Ex Parte Park

Board of Patent Appeals and Interferences

Mar 2, 2009

10135211 (B.P.A.I. Mar. 2, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JAEJIN PARK
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Appeal 2009-0397
Application 10/135,211
Technology Center 2600
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Decided:1 March 3, 2009
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Before MAHSHID D. SAADAT, ROBERT E. NAPPI, and JOHN A.
JEFFERY, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 CFR § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-0397
Application 10/135,211

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1-4, 6-12, 14-20, and 23-25. We have jurisdiction under
35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellant invented a complementary metal oxide semiconductor
(CMOS) image sensor that includes a pixel sensor array having dark pixel
sensors. The image sensor includes a dark level compensation circuit that
controls the analog reference signal or provides a feedback offset for the
analog-to-digital converter (ADC). The ADC compares analog image
signals from the sensor array to a controlled reference signal. This
compensates for process, temperature, and power supply variations.2
Independent claim 1 is reproduced below:

1. A complementary metal oxide semiconductor (CMOS) image
sensor, comprising:

a CMOS pixel sensor array comprising a plurality of
rows of CMOS pixel sensors that produce analog image signals,
the CMOS pixel sensors comprising a plurality of dark pixel
sensors that produce respective analog dark pixel image signals;

an analog-to-digital converter (ADC) circuit that
compares the analog image signals to an analog reference signal
to convert the analog image signals produced by the CMOS
pixel sensors to digital image signals comprising digital dark
pixel image signals generated from the analog dark pixel image
signals; and

2 See generally Spec. 2:5-15, 2:32-3:10, and 5:26-6:24.
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Application 10/135,211

a dark level compensation circuit that controls the
reference signal responsive to an aggregate dark level metric
derived from the digital dark pixel image signals.

The Examiner relies upon the following as evidence in support of the
rejection:
Yiannoulos US 5,982,318 Nov. 9, 1999
Bilhan US 6,791,607 B1 Sep. 14, 2004
(filed Nov. 1, 2000)

1. Claims 1-4, 6-9, 11, 12, 14-16, 18-20, and 23-253 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Yiannoulos and Bilhan
(Ans. 4-21).
2. Claims 10 and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Yiannoulos, Bilhan, and Official Notice4 (Ans. 10, 11,
and 14-16).
Rather than repeat the arguments of Appellant or the Examiner, we
refer to the Brief and the Answer5 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellant. Arguments, which Appellant could have made but did not make
in the Brief, have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).

3 The Examiner mistakenly included canceled claim 13 in the heading of the
rejection (Ans. 4). We presume this claim was not intended to be rejected
for purposes of this decision and deem the error harmless.
4 While claims 10 and 17 are not placed under a separate heading (Ans. 4),
the rejection of these claims clearly introduces the taking of Official Notice.
See Ans. 10, 11, and 14-16.
5 Throughout this opinion, we refer to (1) the Appeal Brief filed May 22,
2007 and (2) the Examiner’s Answer mailed August 22, 2007.
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Application 10/135,211

REJECTION OVER YIANNOULOS AND BILHAN
Claims 1-4, 6, 7, and 9
Regarding representative independent claim 1,6 the Examiner finds
that the combination of Yiannoulos and Bilhan teaches all the recited
elements, including a dark level compensation circuit (Ans. 4-7). Appellant
argues that: (1) the reference signal in Bilhan is added to and not compared
with its analog image signal as recited in claim 1, and (2) there is no
rationale for combining Bilhan with Yiannoulos as the Examiner proposes
(Br. 5-9).

ISSUE
The following issue has been raised in the present appeal:
Has Appellant shown that the Examiner erred in combining Bilhan
with Yiannoulos to teach including a dark level compensation circuit in
rejecting claim 1 under § 103(a)?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
Yiannoulos
1. Yiannoulos discloses a CMOS image sensor (10, 20, and 34)
including a CMOS pixel sensor array 10 having a plurality of rows of

6 Appellant argues claims 1-4, 6, 7, and 9 as a group (Br. 5-9). Accordingly,
we select independent claim 1 as representative. 37 C.F.R. §
41.37(c)(1)(vii).
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pixel sensors and a single slope ADC circuit 34 (Yiannoulos, col. 2, ll.
45-50, col. 3, ll. 38-44, and col. 6, ll. 19-27; Fig. 3).
2. Yiannoulos discloses the sensor array includes blinded cells or pixel
sensors (Yiannoulos, col. 7, l. 62 - col. 8, l. 64).
3. Yiannoulos’ ADC circuit 34 compares at comparator 30 analog image
signals with a reference signal (RAMP) from ramp generator circuit
20 (Yiannoulos, col. 6, ll. 19-48; Fig. 3).
4. Yiannoulos teaches that several ramp generators for each image
sensor array can be used to create averages of offsets and to track
better the spatial variation of a photo integrator’s offsets in a manner
well known in the imaging art (Yiannoulos, col. 8, ll. 59-64).

Bilhan
5. Bilhan teaches a feedback loop or black level offset correction circuit
(512, 514, 516, and 518) used with a CCD signal processing system
(Bilhan, Abstract and col. 4, ll. 27-32 and 52-60; Fig. 5).
6. Bilhan teaches the circuit is used to correct the black level of an image
generated by an image sensor (Bilhan, col. 4, ll. 13-26, 28-39, and 50-
51)
7. Bilhan’s circuit outputs the difference between a digital average of
dark pixel image signals and a black reference value (Bilhan, col. 3, ll.
9-13 and col. 4, ll. 35-40 and 52-61).
8. Bilhan’s circuit: (a) provides an error signal that modifies the existing
analog signal to produce a desired optical black level output at the
ADC, (b) is a highly programmable offset circuit, and (c) improves
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the dynamic range for image processing (Bilhan, col. 3, ll. 19-27 and
40-46).

PRINCIPLES OF LAW
Discussing the question of obviousness of a patent that claims a
combination of known elements, KSR Int’l v. Teleflex, Inc., 550 U.S. 398,
127 S. Ct. 1727 (2007), explains:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
ordinary skill can implement a predictable variation, § 103
likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill. Sakraida [v. AG
Pro, Inc., 425 U.S. 273 (1976)] and Anderson's-Black
Rock[, Inc. v. Pavement Salvage Co., 396 U.S. 57 (1969)] are
illustrative—a court must ask whether the improvement is more
than the predictable use of prior art elements according to their
established functions.
KSR, 127 S. Ct. at 1740.
If the Examiner’s burden is met, the burden then shifts to the
Appellant to overcome the prima facie case with argument and/or evidence.
Obviousness is then determined on the basis of the evidence as a whole and
the relative persuasiveness of the arguments. See In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992).
One cannot show nonobviousness by attacking references individually
where the rejections are based on combinations of references. In re Merck
& Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).

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ANALYSIS
Yiannoulos discloses a CMOS image sensor (10, 20, and 34)
including a CMOS pixel sensor array 10 comprising a plurality of rows of
pixel sensors and an ADC 34 (FF 1). Additionally, Yiannoulos discloses
that the sensor array includes a plurality of dark pixel sensors (FF 2), and the
ADC 34 compares analog image signals with a reference signal (FF 3).
Appellant does not dispute that Yiannoulos teaches these features (Br. 5-9).
The Examiner admits that Yiannoulos does not disclose digital dark
pixel image signals generated from the analog dark pixel image signals and a
dark level compensation circuit as recited in claim 39. For these missing
features, Bilhan is cited (Ans. 6 and 7). Appellant argues that Bilhan does
not teach the above missing features because the reference signal in Bilhan
is not “used for comparison in an ADC” (Br. 6). While we agree that the
reference signal in Bilhan is not used for comparison, one cannot show
nonobviousness by attacking Bilhan individually where, as in the instant
case, the rejection is based on the combination of Yiannoulos and Bilhan.
See Merck, 800 F.2d at 1097. As the Examiner explains (Ans. 22),
Yiannoulos discloses the features of the ADC circuit comparing the analog
signal to a reference signal (FF 3). Bilhan has been cited to teach integrating
a dark level compensation circuit (FF 5) with the existing ramp generator 20
of Yiannoulos to adjust the reference signal (RAMP) fed into the ADC
circuit of Yiannoulos.
Appellant further argues the Examiner fails to provide a reason to
combine Yiannoulos and Bilhan (Br. 6-8). Bilhan teaches such a circuit (FF
5) is used as feedback to correct the black level of an image generated by an
image sensor (FF 6) and is responsive to an aggregate dark level metric (e.g.,
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the difference between the digital average and a black reference level)
derived from digital dark pixel image signals (FF 7). Bilhan provides
numerous reasons for including this circuit, such as producing the desired
optical black level output at the ADC, designing a more programmable
offset circuit, and improving the dynamic range of the image processing (FF
8). Thus, one skilled in the art would have recognized Bilhan’s teaching
would improve Yiannoulos’ image sensor by designing an offset or ramp
generator circuit that produces the desired optical black level output at the
ADC. Such an arrangement for Yiannoulos’ ramp generator would
predictably improve the dynamic range of the system and provide for a more
programmable offset circuit. (Id.) See KSR, 127 S. Ct. at 1740. Moreover,
Yiannoulos teaches using several offset generators for an image sensor array
to generate averages of offsets and to track better the spatial variation of the
photo integrator’s offsets in a manner well known in the imaging art (FF 4).
One skilled would have therefore equally recognized that including Bilhan’s
known offset generator with Yiannoulos’ ramp generator would, among
other things, allow for averages of offsets and more effectively track the
spatial variation of offsets in Yiannoulos’ photo integrator.
Moreover, Appellant has not demonstrated that combining Yiannoulos
with Bilhan would restrict skilled artisans to the specific placement of
Bilhan’s circuit as Appellant suggests (Br. 7 and 8). While Appellant has
provided one possible arrangement, this does not preclude other
arrangements or demonstrate that arranging the Bilhan circuit as proposed
by the Examiner would render the Yiannoulos’ image sensor unsatisfactory
for its intended purpose. To the contrary, Yiannoulos teaches that including
the offsets would only improve the device (FF 4), and Bilhan provides ample
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reasons (FF 8), as discussed above, to integrate a dark level compensation
circuit with Yiannoulos’ image sensor. We, therefore, are not persuaded that
Yiannoulos and Bilhan provide no teaching or suggestion to meet the
limitations of claim 1.
For the above reasons, Appellant has not shown the Examiner erred in
rejecting claims 1-4, 6, 7, and 9 under 35 U.S.C. § 103(a) as being
unpatentable over Yiannoulos and Bilhan.

Claims 11, 12, 14, 18-20, and 23-25
Appellant states that representative independent claims 11, 19, and
237 are patentable for similar reasons discussed in connection with claim 1
(Br. 8) and refers to that discussion (Br. 9). We are not persuaded by
Appellant’s argument, however, for the reasons outlined above with regard
to claim 1. Additionally, apart from merely asserting that certain claim
limitations of claims 11, 19, and 23 are not found in the combination of
Yiannoulos and Bilhan, Appellant does not specifically address the
Examiner’s positions articulated in the Answer (Ans. 11-13 and 16-20) or
explain why these positions are deficient. Merely pointing out what claims
11, 19, and 23 recite is also not considered an argument for separate
patentability of the claim. 37 C.F.R. § 41.37(c)(1)(vii). Such conclusory
statements fall well short of rebutting the Examiner’s prima facie case of
obviousness articulated in the rejection – a position that we find reasonable.

7 Appellant groups: (a) claims 11, 12, 14, and 18; (b) claims 19 and 20; and
(c) claims 23-25 (Br. 8 and 9). Accordingly, we select independent claims
11, 19, and 23 as representative. 37 C.F.R. § 41.37(c)(1)(vii).
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For the above reasons, Appellant has not shown the Examiner erred in
rejecting claims 11, 19, and 23 under 35 U.S.C. § 103(a) as being
unpatentable over Yiannoulos and Bilhan. The rejection of claims 12, 14,
18, 20, 24, and 25 are also sustained because they depend directly or
indirectly from independent claims 11, 19, and 23.

Claims 8, 15, and 16
Representative claim 88 recites the reference signal comprises a ramp
signal provided to a comparator of a single-slope ADC circuit and the offset
signal controls an offset of the ramp signal. The Examiner finds the
combination of Yiannoulos and Bilhan teaches these limitations (Ans. 9).
Appellant repeats the argument that the combination of Yiannoulos and
Bilhan fails to teach generating a reference or ramp signal for an ADC (Br.
9). We are not persuaded by Appellant’s argument for the same reasons
discussed above with regard to claims 1 and 11. This argument also fails to
persuasively rebut the Examiner’s prima facie case of obviousness – a
position we find reasonable.
For the above reasons, Appellant has not shown the Examiner erred in
rejecting claims 8, 15 and 16 under 35 U.S.C. § 103(a) as being unpatentable
over Yiannoulos and Bilhan.

8 Claim 8 depends indirectly from claim 1, and claim 15 depends from claim
11. Appellant, however, does not separately argue claim 15 with
particularity. Additionally, claim 16 has not been separately argued (Br. 5-
9). Accordingly, we group these claims together and select claim 8 as
representative. 37 C.F.R. § 41.37(c)(1)(vii).
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REJECTION OVER YIANNOULOS, BILHAN, AND OFFICIAL NOTICE

Because claims 10 and 17 are rejected based on the combination of
Yiannoulos, Bilhan, and Official Notice (Ans. 10, 11, and 14-16), we
address these claims separately. However, Appellant has not presented
specific arguments with respect to these claims. We are therefore not
persuaded the Examiner erred in finding the combination teaches the
limitations of claims 10 and 17 for the reasons discussed above with regard
to claims 1 and 11. Accordingly, we will sustain the obviousness rejection
of claims 10 and 17 as being unpatentable over Yiannoulos, Bilhan, and
Official Notice.

CONCLUSION
For the foregoing reasons, Appellant has not shown that the Examiner
erred in combining Bilhan with Yiannoulos to teach including a dark level
compensation circuit in rejecting claim 1 under 35 U.S.C. § 103(a).

DECISION
The decision of the Examiner to reject claims 1-4, 6-12, 14-20, and
23-25 is affirmed.
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No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD

MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH, NC 27627
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