Ex Parte Park

Board of Patent Appeals and Interferences

Jul 21, 2009

10304704 (B.P.A.I. Jul. 21, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JUNG SIK PARK
____________

Appeal 2009-003049
Application 10/304,704
Technology Center 2600
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Decided:1 July 21, 2009
____________

Before JOHN A. JEFFERY, KARL D. EASTHOM,
and CARL W. WHITEHEAD, JR., Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-003049
Application 10/304,704

2
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1-3, 5, 6, 8, 10-12, 14, 16-18 and 20.2 See App. Br. 5.
We have jurisdiction under 35 U.S.C. § 6(b) (2002). We reverse.

STATEMENT OF THE CASE
Appellant invented a line-on-glass liquid crystal display that reduces
signal voltage differences caused by line resistances of the line-on-glass type
patterns.3
Claims 1 and 5 which further illustrate the invention follows:
1. A line-on-glass liquid crystal display device, comprising:
a picture display area having a plurality of liquid crystal cells arranged
at crossings of a plurality of gate lines and a plurality of data lines;
a plurality of gate driver integrated circuits for driving the gate lines
mounted on a plurality of gate tape carrier packages, each of plurality of gate
driver integrated circuits including a plurality of stages for sequentially
driving the gate lines using a control signal generated by a timing controller,
each of the plurality of consecutive stages being electrically connected to
one of the plurality of gate lines;
a plurality of data driver integrated circuits for driving the data lines
mounted on a plurality of data tape carrier packages; and
a plurality of line-on-glass signal lines provided at an outer portion of
the picture display area for applying driving signals to the gate driver
integrated circuits,

2 The rejection of claims 8-10 and 14 under 35 U.S.C. § 112, first paragraph;
as well as the rejection of claims 9 and 15 under 35 U.S.C. § 102 (e) have
been withdrawn by the Examiner (Ans. 2).
3 See generally App. Br. 7.
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wherein each of plurality of gate driver integrated circuits includes a
plurality of gate input line resistors each connected to one of the plurality of
the stages, each of the plurality of gate input line resistors having a
resistance value corresponding to the gate line it is connected to, wherein
resistance values of successive gate input line resistors increases by a
predetermined amount, the predetermined amount being selected such that
an input line resistance value of the last gate line connected to each gate
driver integrated circuit is substantially equal to an input line resistance
value of the first gate line connected to a successive gate driver integrated
circuit due to a line resistance of the line-on-glass signal line group between
the gate driver integrated circuits.
Claim 5 which further illustrates the invention follows:
5. A liquid crystal display device, comprising:
a plurality of gate lines;
a plurality of driver integrated circuits connected to the plurality of
gate lines; and
a plurality of consecutive stages for sequentially driving the gate lines
using a control signal generated by a timing controller, each of the plurality
of consecutive stages within each of the plurality of driver integrated
circuits, each of the plurality of consecutive stages being electrically
connected to one of the plurality of gate lines; and
a plurality of resistors each connected to one of the plurality of stages,
wherein a line resistance of successive ones of the plurality of stages is
incrementally increased by a predetermined amount, the predetermined
amount being selected such that a line resistance at a last one of the
consecutive stages within one of the plurality of driver integrated circuits is
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substantially equal to a line resistance at a first one of consecutive stages
within a successive one of the plurality of driver integrated circuits due to a
line resistance of a signal line group between the plurality of driver
integrated circuits.

The Rejections
The Examiner relies upon the following prior art reference as
evidence of unpatentability:
Choi US 5,657,041 Aug. 12, 1997
Watanabe US 5,870,163 Feb. 9, 1999
Kang US 6,621,547 B2 Sep. 16, 2003
Kim US 6,639,589 B1 Oct. 28, 2003

Claims 5, 6, 8, 10-12, 14, 16, 17 and 20 stand rejected under 35
U.S.C. § 102(e) as being unpatentable over Kang (Ans. 3-6).
Claims 1, 3 and 18 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kang, Kim and Watanabe (Ans. 6-9).
Claim 2 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kang, Kim, Watanabe and Choi (Ans. 9-10).
Rather than repeat the arguments of Appellant or the Examiner, we
refer to the Briefs and the Answer for their respective details. In this
decision, we have considered only those arguments actually made by
Appellant. Arguments which Appellant could have made but did not make
in the Briefs have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii) (2008).

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5
The Anticipation Rejection
Appellant argues that Kang’s resistances, R1, R2 . . . , Rn are intrinsic
resistances associated with the gate-driving signal output lines and therefore
the Examiner’s reliance upon Kang’s resistances to disclose the claimed
plurality of resistors is erroneous. See App. Br. 11. It is the Examiner’s
position that Kang’s placement of the resistances between adjacent gate lines
or stages is a fair teaching of the plurality of resistors claimed by the
Appellant (Ans. 11).

ISSUE
Has the Appellant shown that the Examiner erred in finding that Kang
discloses a line-on-glass liquid crystal display having a plurality of resistors
connected to stages wherein the line resistance of successive stages increase
incrementally to where the line resistances of the first and last stages are
substantially equal?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
Kang

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1. Figure 4 of Kang is reproduced below:

Figure 4 discloses a TFT substrate driving signal timing module of a
liquid crystal display.

2. Kang discloses that the level of the output signals from the gate driving
signal output lines 334 connected to the gate lines 353 can be adjusted by
using the intrinsic resistance of the first and second signal transmitting
patterns 314 and 316, signal transmitting line 313 and an internal resistance
of the gate driving IC 332 to prevent separation of a LCD screen (col. 10, ll.
1-7).

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3. Table 2 of Kang is reproduced below:

Table 2 discloses the resistance at various points of the liquid crystal
display depicted in Figure 4. Intrinsic resistances (R1+R2 . . . Rn) are
also disclosed.

4. Kang discloses intrinsic resistances exist inside of the gate driving signal
output lines 334 and the gate driving signal output lines 334a of the gate
driving ICs 332 and 332a are defined as R1, R2 . . . Rn (col. 11, ll. 5-8).
5. Kang discloses that in order to minimize the difference between the
resistance Voff last applied to the last gate line 353b of the first gate driving
signal timing module 330 and the resistance Voff last applied to the first gate
line 353c of the second gate driving signal timing module 300a, Voff must
have a linear increasing magnitude when being applied to the gate lines
connected to the gate driving IC 332 (col. 11, ll. 60-67).
6. Kang also discloses that a reduction in the difference between the signal
Voff last applied to the last gate line 353b of the first gate driving signal timing
module 330 and the signal Voff last applied to the first gate line 353c of the
second gate driving signal timing module 330a requires that the gate driving
signal transmitting line 335 shifts the resistance Voff to control the variation
of brightness between the first gate driving timing module 330 and the
second gate driving timing module 330a (col. 11, l. 67; col. 12, ll. 1-13).

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PRINCIPLE OF LAW
Anticipation is established only when a single prior art reference
discloses, expressly or under the principles of inherency, each and every
element of a claimed invention as well as disclosing structure which is
capable of performing the recited functional limitations. RCA Corp. v. Appl.
Dig. Data Sys., Inc., 730 F.2d 1440, 1444 (Fed. Cir. 1984); W.L. Gore &
Assoc., Inc. v. Garlock, Inc., 721 F.2d 1540, 1554 (Fed. Cir. 1983).

ANALYSIS
Appellant argues that the Examiner’s identification of Kang’s
resistances (R1+R2 . . . Rn) as a plurality of resistors connected to one of the
plurality of stages is incorrect (App. Br. 11). Appellant further argues that
the resistances are intrinsic and are therefore actually part of the output stage
rather that being connected to the stage as claimed (App. Br. 11). The
Examiner disagrees and argues that in Figure 4 of Kang, the resistances R1,
R2 . . . , Rn are disposed between adjacent gate lines or stages and therefore
Kang teaches a plurality of resistors connected to one of the plurality of
stages as claimed (Ans. 11).
We do not find support in Kang for the Examiner’s position that
Figure 4 discloses resistors such as R1, R2 . . . , Rn disposed between
adjacent gate lines or stages to address Kang’s concerns with the variation of
brightness in an LCD device. See FF 1-6. Kang does not rely upon resistors
connected to a plurality of stages to reduce the difference between the signal
applied to the last gate line 353b of the first gate driving signal timing
module 330 and the signal applied to the first gate line 353c of the second
gate driving signal timing module 330a. See FF 2, 5 and 6.
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Kang discloses that R1, R2 . . . Rn are intrinsic resistances and are
therefore considered to be electrical characteristics of the gate driving signal
output lines. See FF 1, 3 and 4. Thus, Kang’s R1, R2 . . . Rn resistances are
not incrementally increasing resistors connected to a plurality of stages as
required in claim 5. See FF 1 and 3. Kang’s resistances increase as the
number of gate driving signal output lines increase as a result of the
summation of the output lines (FF 1, 3). Therefore, we agree with the
Appellant’s argument that since Kang’s resistances are intrinsic they are not
resistors connected to the plurality of stages as required by the claim 5.
Claim 11 also requires a plurality of resistors connected to a plurality
of stages and we have concluded that Kang does not disclose this feature.
Therefore, we will not sustain the Examiner’s rejection of independent
claims 5 and 11 and dependent claims 6, 8, 10, 12, 14, 16, 17 and 20 for
similar reasons.

The Obviousness Rejections
PRINCIPLE OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). In so
doing, the Examiner must make the factual determinations set forth in
Graham v. John Deere Co., 383 U.S. 1, 17 (1966). If the Examiner's burden
is met, the burden then shifts to the Appellant to overcome the prima facie
case with argument and/or evidence. Obviousness is then determined on the
basis of the evidence as a whole and the relative persuasiveness of the
arguments. See In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).
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ANALYSIS
Claim 1 also requires a plurality of resistors connected to a plurality of
stages and we have concluded that Kang does not disclose this feature. We
will not sustain the Examiner’s rejection of claim 1. Since the other cited
references to Kim, Watanabe and Choi do not cure the deficiencies of Kang
noted above with respect to independent claim 1, we will also not sustain the
Examiner’s obviousness rejections of dependent claims 2, 3 and 18 for
similar reasons.

CONCLUSION
Appellant has shown that the Examiner erred in finding that Kang
discloses a line-on-glass liquid crystal display having a plurality of resistors
connected to stages wherein the line resistance of successive stages increase
incrementally to where the line resistances of the first and last stages are
substantially equal.

ORDER
We will not sustain the Examiner’s decision rejecting claims 1-3, 5, 6,
8, 10-12, 14, 16-18 and 20.
REVERSED

KIS
MCKENNA LONG & ALDRIDGE, L.L.P.
1900 K STREET, NW
WASHINGTON, DC 20006