Ex Parte Park

Board of Patent Appeals and Interferences

Apr 29, 2010

11327681 (B.P.A.I. Apr. 29, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte JAE-KWAN PARK
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Appeal 2009-001793
Application 11/327,681
Technology Center 2800
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Decided: April 29, 2010
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Before ROBERT E. NAPPI, KENNETH W. HAIRSTON, and
JOHN C. MARTIN, Administrative Patent Judges.

HAIRSTON, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-001793
Application 11/327,681

2
This is an appeal under 35 U.S.C. §§ 6(b) and 134 from the final
rejection of claims 11, 12, 18, and 19.
The disclosed invention relates to a pulse generator (Fig. 7; Spec. 7, 8,
14-16; Abstract).
Claim 11 is representative of the claims on appeal, and it reads as
follows:
11. A pulse generator, comprising:
a reference current generating circuit that is configured to generate a
reference current;
a charge circuit that is configured to be charged through a first
mirroring current that is produced by mirroring the reference current in
response to an input signal;
a discharge circuit that is configured to be discharged through a
second mirroring current that is produced by mirroring the reference current
in response to an output signal of the charge circuit; and
a logic circuit that is configured to generate a pulsed output signal
having a pulse width that is substantially proportional to a power supply
voltage in response to the input signal and an output signal of the discharge
circuit.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yamaki US 6,643,193 B2 Nov. 4, 2003
The Examiner rejected claims 11, 12, 18, and 19 under 35 U.S.C. §
102(b) based upon the teachings of Yamaki.
Turning first to the anticipation rejection of claim 11, the Examiner
contends (Ans. 3, 4) that Figure 11 of Yamaki shows all of the pulse
Appeal 2009-001793
Application 11/327,681

3
generator structure set forth in this claim. Appellant argues (App. Br. 4, 5)
that:
[T]he identified “charge circuit” (namely inverter 31 and
capacitor Cr2) of Yamaki is not “charged through a first
mirroring current that is produced by mirroring the reference
current in response to” the “start signal” of Figure 11.
Instead, the capacitor Cr2 of Yamaki is charged through a
current that is produced in response to the signal vtri. (See
Yamaki at Col. 14, lines 24-32 and Fig. 11). Yamaki also
clearly identifies the function of the “start signal” described
therein, which is to control where the oscillation signal starts
and stops. (Yamaki at Col. 14, lines 37-39 and Fig. 11).
Accordingly, the rejection of claim 11 as anticipated by Yamaki
should be reversed as the “start signal” of Yamaki does not
correspond to the “input signal” of Claim 11.
(App. Br. 5).
In response, the Examiner indicates (Ans. 7, 8) that the start signal in
Figure 11 of Yamaki inputs the inverter INV1 through the NAND gate
NAND1, and “causes a first mirroring current, current through M4 in Figure
11, to flow that is used to charge the charge circuit.”
Inasmuch as nothing in claim 11 on appeal precludes the inclusion of
the NAND gate NAND1 between the input signal (i.e., the start signal) and
the circuit configured to be charged (i.e., inverter INV1 and capacitor Cr2),
we agree with the Examiner’s conclusion that Yamaki shows all of the
circuit structure in claim 11.
In summary, the anticipation rejection of claim 11 is sustained
because each and every limitation in claim 11 is found either expressly or
inherently in Yamaki. In re Crish, 393 F.3d 1253, 1256 (Fed. Cir. 2004).
The anticipation rejection of claim 12 is sustained because Appellant
has not presented any patentability arguments for this claim.
Appeal 2009-001793
Application 11/327,681

4
Turning next to the anticipation rejection of claim 18, Appellant
argues (Reply Br. 2) that claim 18 is not anticipated by Figure 11 of Yamaki
because the circuit path proposed by the Examiner (Ans. 5) of a second
inverter (i.e., INV2) coupled to an output terminal of the first inverter (i.e.,
INV1) does not electrically connect the second current source (i.e., transistor
M2) and the first reference voltage (i.e., vtri) because the gate of transistor
M8 will block the current flow to the second current source (i.e., transistor
M2). We agree with Appellant’s argument that the gate of transistor M8
will block current flow/electrical connection between the second current
source M2 and the first reference voltage vtri in Yamaki. Accordingly, the
anticipation rejection of claims 18 and 19 is reversed.
In summary, the decision of the Examiner is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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