Ex Parte Palomar et al

Board of Patent Appeals and Interferences

Aug 3, 2011

11280554 (B.P.A.I. Aug. 3, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ARMANDO PALOMAR, RONALD K. KREUZENSTEIN,
and RONALD N. HILTON
____________

Appeal 2009-011698
Application 11/280,554
Technology Center 2100
____________

Before LANCE LEONARD BARRY, JOHN A. JEFFERY,
and ST. JOHN COURTENAY III, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 3-8, 10-15, and 17-20. We have jurisdiction under
35 U.S.C. § 6(b). We reverse.

STATEMENT OF THE CASE
Appellants’ invention caches memory of a mainframe computer
system to distributed shared input/output cache subsystems. See generally
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Spec. ¶ 0001; Abstract. Claim 1 is illustrative with key disputed limitations
emphasized:
A method comprising:

accessing a first set of shared data storage units with a first
mainframe computer system having a first central processor and an
associated first cache, the first mainframe computer system directly
coupled to the first set of shared data storage units;

accessing the first set of shared data storage units with a second
mainframe computer system having a second central processor and an
associated second cache, the second mainframe computer system
directly coupled to the first set of shared data storage units; and

communicating at a physical level between the first mainframe
computer system and the second mainframe computer system via a
high speed network.

The Examiner relies on the following as evidence of unpatentability:
Lenk US 6,098,156 Aug. 1, 2000
Benkual US 2004/0073623 A1 Apr. 15, 2004

THE REJECTIONS
1. The Examiner rejected claims 1, 3-6, 8, 10-13, 15, and 17-19 under
35 U.S.C. § 102(b)1 as anticipated by Benkual. Ans. 4-6.2

1 This reference technically qualifies as prior art under §§ 102(a) and (e)
since it was published less than a year before Appellants’ effective filing
date (November 15, 2004) based on a provisional application. We
nonetheless deem the Examiner’s error harmless since it does not affect our
assessment of the merits of the anticipation rejection.
2 Throughout this opinion, we refer to (1) the Appeal Brief filed November
20, 2008 (supplemented January 16, 2009); (2) the Examiner’s Answer
mailed March 17, 2009; and (3) the Reply Brief filed May 13, 2009.
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2. The Examiner rejected claims 7, 14, and 20 under 35 U.S.C. § 103(a)
as unpatentable over Benkual and Lenk. Ans. 6-7.

THE ANTICIPATION REJECTION
Regarding independent claim 1, the Examiner finds that Benkual
directly couples two “mainframe computer systems” (processors 202 and
204) to shared data storage units (main memory 216) to access those units,
where the mainframes3 communicate at a physical level via a network as
claimed. Ans. 4-5.
Appellants argue that Benkual does not disclose multiple mainframes
that (1) share storage units, and (2) communicate with each other at a
physical level as claimed, but rather uses one system with two processors
coupled via an internal bridge. App. Br. 6-10; Reply Br. 5-10. Appellants
add that Benkual does not directly couple the processors to shared memory,
but rather to an intervening bridge. App. Br. 9; Reply Br. 9. The issue
before us, then, is as follows:

ISSUE
Under § 102, has the Examiner erred in rejecting claim 1 by finding
that Benkual directly couples two mainframes to shared data storage units to
access those units, where the mainframes communicate at a physical level
via a network?

3 For brevity, we refer to the recited “mainframe computer systems” as
“mainframes.”
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FINDINGS OF FACT (FF)
1. Benkual’s multiprocessor system supports cache coherence
operations. To this end, processors 202, 204 (and their respective CPUs
206, 210 and cache 208, 212) are coupled to bridge 214 via unidirectional,
point-to-point interconnections. Benkual, ¶¶ 0028-29; Fig. 2. Benkual’s
multiprocessor system in Figure 2 is reproduced below:

Benkual’s multiprocessor system in Figure 2

2. The bridge “reflects” commands by transmitting copies of read and
write commands to the processors. Benkual, ¶¶ 0030, 0034; Figs. 2-3.

ANALYSIS
This appeal hinges on whether Benkual’s processors, which the
Examiner maps in the rejection to the recited “mainframes,” are directly
coupled to the main memory (i.e., the shared data storage units). As
explained below, they are not.
We reach this conclusion noting that claim 1 unambiguously requires
direct coupling—a requirement that excludes indirect coupling via
intervening circuitry or components. Indeed, this distinction between direct
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and indirect coupling was recently addressed by the Federal Circuit which
found no error in construing the recited term “electrically coupled” as
“arranged so that electrical signals may be passed either directly, or
indirectly via intervening circuitry, from one component to another.” Mems
Tech. Berhad v. Int’l Trade Comm’n, No. 2010-1018, 2011 WL 2214091
(Fed. Cir. 2011) (unpublished), at *6-9. Notably, the court declined to limit
the recited electrical coupling to direct electrical coupling in view of the
term’s plain meaning noted above. Id. at *7-9.
The clear import of this discussion is that direct coupling has no
intervening circuitry or components, unlike indirect coupling. And that
distinction highlights the fundamental flaw in the Examiner’s rejection, for
the Examiner asserts in the rejection that Benkual’s processors 202 and 204
(which are said to be “mainframes”) are directly coupled to main memory
216 (i.e., shared data storage units). Ans. 4-5. But as Appellants indicate
(App. Br. 9-10; Reply Br. 9-10), the bridge (which “reflects” commands to
the processors) is located between the processors and the main memory. FF
1-2. Therefore, the processors are, at best, indirectly coupled to the main
memory via this intervening bridge. So even assuming, without deciding,
that the processors somehow necessarily constitute “mainframes” as the
Examiner asserts—an inherency position undercut somewhat by the term’s
plain meaning which indicates a large, high-level, computationally-intensive
computer supporting many users via terminals4—the processors are still not
directly coupled to the shared data storage units as claimed.

4 A “mainframe computer” is “[a] high-level, typically large and expensivie
computer designed to handle intensive computational tasks. Mainframe
computers are characterized by their ability to support many users connected
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In the Response to Arguments section of the Answer, however, the
Examiner asserts that this direct connection is met since the bridge is
coupled to the processors through unidirectional interconnections, and
therefore each “mainframe” allegedly constitutes a respective processor and
the bridge that are presumably collectively directly coupled to the main
memory. See Ans. 8-9.
This position is problematic. Not only does it map the same element
in the prior art (the bridge) to two different recited elements in the claim—a
dubious claim construction practice5—it represents a clear shift in the
Examiner’s position between that articulated in the rejection (which
unambiguously maps the “mainframes” to solely the processors) to the
Response to Arguments section which apparently abandons that position by
including the bridge in each “mainframe.” Compare Ans. 4 with Ans. 8-9.
Simply put, the Examiner changed the mainframes’ mapping in the rejection
to a different mapping in the Answer’s Response to Arguments.
Not only do we find the Examiner’s new position in the Response to
Arguments substantively problematic, but such shifts run counter to notions
of fundamental fairness in appellate proceedings, for the appeal was taken
based on the Examiner’s position articulated in the rejection—not the

to the computer by terminals.” MICROSOFT COMPUTER DICTIONARY (5th ed.
2002). Accord Reply Br. 8 (citing similar definition of “mainframe” from
another source).
5 When a claim requires plural distinct structural elements, it is improper to
map a single disclosed element to the plural recited elements. See Lantech,
Inc. v. Keip Mach. Co., 32 F.3d 542, 547 (Fed. Cir. 1994); see also In re
Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) (claims requiring three
separate means not anticipated by structure containing only two means using
one element twice).
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Response to Arguments. To the extent that the Examiner decided to
abandon the position in the rejection in favor of another position on appeal,
such a shift must be designated as a new ground of rejection to give
Appellants a fair opportunity to respond to the new position—a procedural
requirement not followed here. See MPEP 1207.03; see also In re Kronig,
539 F.2d 1300, 1302-03 (CCPA 1976).
Although Appellants did not petition this procedural inconsistency,
but instead filed a Reply Brief essentially reiterating their position in the
Appeal Brief, we are nonetheless presented with two inconsistent positions
in the Examiner’s Answer. Although we could decline to reach the merits of
the newer position since it is inconsistent with that taken in the rejection
from which the appeal was taken,6 we nonetheless find that both positions
are problematic for the reasons noted above.
We are therefore persuaded that the Examiner erred in rejecting (1)
independent claim 1; (2) independent claims 8 and 15 which recite
commensurate limitations; and (3) dependent claims 3-6, 10-13, and 17-19
for similar reasons.

THE OBVIOUSNESS REJECTION
Since the Examiner has not shown that Lenk cures the deficiencies
noted above regarding the independent claims, we will not sustain the
obviousness rejection of claims 7, 14, and 20 (Ans. 6-7) for similar reasons.

6 The Board reviews the Examiner’s final rejection in appeals under 35
U.S.C. § 134(a). See In re Webb, 916 F.2d 1553, 1556 (Fed. Cir. 1990).
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CONCLUSION
The Examiner erred in rejecting (1) claims 1, 3-6, 8, 10-13, 15, and
17-19 under § 102, and (2) claims 7, 14, and 20 under § 103.

ORDER
The Examiner’s decision rejecting claims 1, 3-8, 10-15, and 17-20 is
reversed.

REVERSED

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