Ex Parte Palmer

Patent Trial and Appeal Board

Aug 1, 2016

13175388 (P.T.A.B. Aug. 1, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/175,388 07 /01/2011 David A. Palmer
59752 7590 08/03/2016
BROOKS, CAMERON & HUEBSCH , PLLC
1201 MARQUETTE A VENUE SOUTH, SUITE 400
MINNEAPOLIS, MN 55403
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1002.0880001[10-006500US] 2533
EXAMINER
SADLER, NATHAN
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
08/03/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
Micron.Docketing@bipl.net
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID A. PALMER
Appeal2015-002214
Application 13/175,388
Technology Center 2100
Before MAHSHID D. SAADAT, JOHNNY A. KUMAR, and
JON M. JURGOV AN, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appellant 1 appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1-5 and 8-32. 2 We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
1 According to Appellant, the real party in interest is Micron Technology,
Inc. (App. Br. 3).
2 Claims 6 and 7 were canceled.
Appeal2015-002214
Application 13/175,388
STATEMENT OF THE CASE
Introduction
Appellant's invention relates to coalescing unaligned data in
semiconductor memory devices (Spec. if 1 ). Exemplary claim 1 under
appeal reads as follows:
1. A method for unaligned data coalescing, comprising:
receiving a write command comprising a first write
subcommand associated with a first unaligned portion of data, a
second write subcommand associated with a second unaligned
portion of data, and a third write subcommand associated with
an aligned portion of data;
writing the aligned portion of data to a first page in a
memory device, while coalescing the first unaligned portion of
data and the second unaligned portion of data, wherein
coalescing includes writing the first unaligned portion of data
and the second unaligned portion of data to a second page in a
memory device;
storing logical addresses associated \x1ith the first
unaligned portion of data and the second unaligned portion of
data in a coalescing data structure; and
storing an indicator to the first unaligned portion of data
and an indicator to the second unaligned portion of data in the
coalescing data structure.
The Examiner's Rejections
Claims 1-5, 8-18, and 22-32 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Su (US 2010/0287330 Al; Nov. 11, 2010) and Yano (US
2009/0222628 Al; Sept. 3, 2009) (Ans. 2-3; Final Act. 3-24).
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Application 13/175,388
Claims 19--21 are rejected under 35 U.S.C. § 103(a) as unpatentable
over Su, Yano, and Takeshi (JP 2005-141420; June 2, 2005) (Final Act. 25-
26).
Appellant's Contentions
Appellant contends the following:
1. Su does not teach "coalescing the first unaligned portion of data and
the second unaligned portion of data," as recited in independent claims 1, 8,
14, 17, 25, and 30 (App. 10-11; Reply Br. 5). Su does not describe data
D 10 as unaligned data, because D 10 is stored in memory block PBA4,
which is designated for aligned data (id.).
2. Su's separating or storage of unaligned data in a physical memory
block is not analogous to the claimed "coalescing" of unaligned data recited
in claims 1, 8, 14, 17, 25, and 30 (App. Br. 12; Reply Br. 6).
3. Claims 1, 8, 14, 17, 25, and 30 require writing the aligned portion of
data to a first page in a memory device while coalescing the first unaligned
portion of data and the second unaligned portion of data, whereas Su's
alleged aligned data writing step S 1106 does not occur while coalescing
steps Sl 103, Sl 104, and Sl 105 occur (App. Br. 11-12; Reply Br. 5). Yano
fails to cure this deficiency of Su (App. Br. 12-13).
4. Su does not teach "coalescing the unaligned portion of data with data
from a third write command including a logical address corresponding to a
same page of data associated with a logical address of the unaligned portion
of data," as required in independent claims 8 and 17 (App. Br. 12). Yano
fails to cure this deficiency of Su (App. Br. 13).
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Application 13/175,388
5. Claims 1, 8, 14, 17, 25, and 30 require "storing an indicator to the first
unaligned portion of data and an indicator to the second unaligned portion of
data in the coalescing data structure," whereas Y ano teaches a single next
entry pointer, not the claimed multiple different indicators (App. Br. 12). 3
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments (App. Br. 10-17; Reply Br. 5---6) that the Examiner erred. We
disagree with Appellant's above contentions 1-5. We adopt as our own (1)
the findings and reasons set forth by the Examiner in the action from which
this appeal is taken (Final Act. 3-26) and (2) the reasons set forth by the
Examiner in the Examiner's Answer (Ans. 2---6) in response to Appellant's
Appeal Brief. We concur with the conclusions reached by the Examiner.
We highlight and address specific findings and arguments for emphasis as
foiiows.
We are not persuaded of Examiner error by Appellant's contention 1
that Su's data DlO is not described as unaligned data. The Examiner finds
Su's aligned data fills a physical memory page, while not-aligned (i.e.,
unaligned) data does not fill a memory page, which is consistent with
Appellant's description of aligned and unaligned data (see Spec. i-fi-f 16-17:
aligned data portion completely fills logical page, unaligned does not fill
page). We agree with the Examiner's finding that Su's data D02, which fills
only half of page LPA2 (Ans. 3--4 (citing Su i171 and Figs. lOA-lOB)),
3 Separate patentability is not argued for dependent claims 2-5, 9-13, 15-16,
18-24, 26-29, 31, and 32 (App. Br. 16-17). Except for our ultimate
decision, these claims are not discussed further.
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Application 13/175,388
teaches a first unaligned portion of data, and data D 10, which is also shown
filling only half of LPA2 (id.), teaches a second unaligned portion of data.
Appellant's contention 2 that Su's storage of unaligned data in a
physical memory block is not analogous to the claimed "coalescing" of
unaligned data is unpersuasive of error. The Examiner finds, and we agree,
that Su's combination of unaligned portions D02 and DlO into a single, full
memory page teaches "coalescing" (Ans. 3-5 (citing Su i-f 71); see also Su
i-f 75 for description of cited Figs. lOA-lOB: previously stored data D02 is
combined with data DlO), which is consistent with Appellant's description
of "coalescing" of unaligned data (see Spec. i-f 19: data that is coalesced is
written to memory page such that the page is aligned, e.g., the data starts at
the beginning and ends at the end of a page).
As to Appellant's contention 3 that Su does not teach writing an
aligned portion of data to a first page in a memory device while coalescing
the first and second unaligned portions of data, we are not persuaded of
Examiner error. The broadest reasonable interpretation, consistent with
Appellant's disclosure, of writing aligned data "while coalescing" unaligned
portions of data does not require aligned data and unaligned data to be
written simultaneously (see In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
1997) (claim language is given its broadest reasonable interpretation during
prosecution)). Thus, we agree with the Examiner's finding that Su's aligned
data is written while the process of coalescing is pending completion (Ans. 4
(citing Su Fig. 11, steps S 1103-S 1106: coalescing begins when determining
if unaligned data is present (Sl 103), followed by writing aligned data
(S 1106), and then followed by combining unaligned data (S 1105))).
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Application 13/175,388
Appellant's contention 4 is not persuasive of Examiner error, because
we agree with the Examiner's finding that Su teaches a first write command
associated with an unaligned portion of data (i.e., D02, as discussed supra),
and coalescing the unaligned data with data (i.e., D 10) from another, or
third, write command including a logical address corresponding to a same
page of data associated with a logical address of the unaligned portion of
data (i.e., D02 and DlO are combined by writing both onto the same physical
page PPA2 with the same logical address LPA2) (Ans. 3-5 (citing Su i171
and Figs. lOA-lOB)).
Appellant's contention 5 that Yano teaches a single next entry pointer
rather than multiple different indicators is not persuasive of Examiner error,
because Appellant is essentially attacking the reference individually where
the rejection is based on the combination of Su and Yano (see In re Keller,
642 F.2d 413, 426 (CCPA 1981) ("[O]ne cannot show non-obviousness by
attacking references individuaiiy where ... the rejections are based on
combinations of references.")). The Examiner relied on Y ano to teach the
concept of using indicators (i.e., pointers) for each logical data address to
more efficiently manage allocation and access of data (Final Act. 4--5 (citing
Yano i-f 122)), and we agree with the Examiner's finding that the
combination of Su and Y ano teaches storing an indicator for each unaligned
portion of data in the data structure (Final Act. 3-5).
Accordingly, we sustain the Examiner's rejection of independent
claims 1, 8, 14, 17, 25, and 30 under 35 U.S.C. § 103(a).
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DECISION
The Examiner's decision to reject claims 1-5 and 8-32 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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