Ex Parte Pagaila et al

Patent Trial and Appeal Board

Aug 28, 2018

13944825 (P.T.A.B. Aug. 28, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/944,825 07/17/2013
112165 7590 08/30/2018
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
Reza A. Pagaila
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0230 CON 1133
EXAMINER
NADAV,ORI
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
08/30/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte REZA A. P AGAILA, Y AOJIAN LIN, JUN MO KOO, and
HEEJO CHI
Appeal2017-009612
Application 13/944,825 1
Technology Center 2800
Before GEORGE C. BEST, CHRISTOPHER C. KENNEDY, and
SHELDON M. McGEE, Administrative Patent Judges.
McGEE, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellant seeks our review of the
Examiner's rejections of claims 33 and 46-64. Br. 11-25.
We have jurisdiction. 35 U.S.C. § 6.
We affirm.
1 Appellant is the Applicant, STATS ChipPAC, Ltd. STATS ChipPAC Pte.,
Ltd. is identified as the real party in interest. Br. 1.
Appeal2017-009612
Application 13/944,825
BACKGROUND
The subject matter on appeal is directed to methods of making a
semiconductor device. Spec. ,r 2; see also Independent claims 33, 51, and
58.
REJECTIONS
On appeal, the Examiner maintains2 the following rejections under 35
U.S.C. § I03(a):
I. Claims 58, 59, and 61 as unpatentable over Konishi3 in view of
Quek; 4
II. Claims 33, 46, 47, 50-54, 57---61, and 64 as unpatentable over
Quek in view of Konishi and Sekiguchi; 5 and
III. Claims 48, 49, 55, 56, 62, and 63 as unpatentable over Quek in
view of Konishi and Sekiguchi, and further in view of
Fukazawa. 6
Rejection I
Figure 21 from Appellant's Specification illustrates the claimed
subject matter of independent claim 58 and is copied below to provide
context:
2 The Examiner withdrew the rejection of claims 47, 48, 50, 54, 55, and 57-
64 under 35 U.S.C. § 112, ,r 1 as lacking written description. Ans. 2.
3 US 7,301,781 B2, issued Nov. 27, 2007.
4 US 6,492,726 Bl, issued Dec. 10, 2002.
5 US 2008/0128881, published June 5, 2008.
6 US 2007/0007639 Al, published January 11, 2007.
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Application 13/944,825
330
~
334
280
270 334
268 254
262 276
FIG. 21
Figure 21 "illustrates an upper interposer stacked over a lower
interposer with openings for containing two semiconductor die[s]." Spec.
Claim 58 recites:
A method of making a semiconductor device, comprising:
providing a first substrate [244] including a first
conductive via formed through the first substrate;
disposing a first semiconductor die [252] over the first
substrate with a bump [256] formed on an active surface of the
first semiconductor die contacting the first conductive via of the
first substrate;
disposing a second substrate [332] in direct contact with
the first substrate and around the first semiconductor die while
maintaining separation between the second substrate and first
semiconductor die, wherein the second substrate includes a
second conductive via formed through the second substrate;
forming a first interconnect structure [274] over a surface
of the first substrate opposite the second substrate; and
depositing an encapsulant [270] over the first
semiconductor die and first substrate.
Br. 30-31 (reference numbers inserted).
In rejecting claim 58, the Examiner finds that Konishi discloses each
of the recited method steps, and that although Konishi shows "a second
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Application 13/944,825
substrate ( the upper part of layer 2) in direct contact with the first substrate
[ the lower part of layer 2] and around the first semiconductor die," Konishi
does not expressly recite a method step of "disposing" such second substrate
around the first semiconductor die. Final Act. 3--4 ( citing Konishi Fig. 4
"and related text"). The Examiner, however, finds that Konishi discloses
"that module board 2 is formed by laminating a plurality of dielectric layers
in direct contact with each other." Ans. 6 (citing Konishi 4:66-5: 10). Thus,
the Examiner determines that Konishi' s "structure is formed by using a
process identical to the process recited in claim 5 8" despite Konishi' s lack of
express disclosure of the term "disposing" the substrates as claimed. Ans. 6.
The Examiner finds further that Konishi does not disclose that the first
semiconductor die has a bump formed on the active surface as recited in
claim 58 and relies on Quek's disclosure to address this deficiency. Final
Act. 4. Specifically, the Examiner finds that "Quek [teaches] in figure 1 and
related text a first semiconductor die 10 having a bump 11' formed on the
active surface." Id. Based on this disclosure, and because Konishi and
Quek are from the same field of endeavor, the Examiner concludes that it
would have been obvious to incorporate Quek's active surface bumps "in
order to improve the electrical connections of the device by using well
known conventional pads or bumps." Id. 4--5.
We decide the propriety of the rejection based solely on Appellant's
arguments. See Ex parte Frye, 94 USPQ2d 1072 (BP AI 2010)
(precedential) (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed.
Cir. 2011)).
Appellant contends that Konishi fails to teach or suggest a method
where a second substrate is disposed in direct contact with a first substrate
because Konishi's "module board 2 constitutes one substrate, and the
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Application 13/944,825
Examiner's arbitrary division of module board 2 into first and second
substrates in an attempt to use the one module board to read on two claim
features is improper." Br. 21; see also id. at 23. Thus, Appellant contends
that "Konishi does not describe, and a person skilled in the art would not
consider, the single module board 2 as having a second substrate disposed in
direct contact with the first substrate." Id.
This argument is not persuasive for the reasons well-stated by the
Examiner at pages 5-7 of the Answer, which we adopt as our own. We
emphasize here that Appellant has not challenged the Examiner's position as
set forth in the Answer, i.e., no Reply Brief has been filed.
Appellant also contends that the skilled artisan would not have been
motived to apply Konishi's sealing portion 3 to Quek's semiconductor
device 14, and that the Examiner has failed to provide a "reasonable
rational[ e] to introduce sealing portion 3 from Konishi into the Quek
package." Br. 23-24. This argument is not persuasive for several reasons.
First, it does not address the rejection as set forth by the Examiner. Namely,
the Examiner does not propose introducing Konishi' s sealing into the device
of Quek. Rather, the Examiner indicates that it would have been obvious to
modify Konishi's device with Quek's "well known conventional pads or
bumps." Final Act. 4--5. Furthermore, in the Answer, the Examiner
distinguishes Quek's protection of a semiconductor device vis-a-vis
Konishi' s sealing of such a device, and concludes that sealing would be
more advantageous than mere protection. Ans. 9-10. This determination
goes uncontested by Appellant. Therefore, on this record, we cannot agree
with Appellant that protection and sealing of a semiconductor device would
be "technically duplicative" as alleged. Br. 23-24.
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Application 13/944,825
Because Appellant fails to identify error in the Examiner's rejection of
independent claim 58, we sustain the rejection of this claim, as well the
rejection of dependent claims 59 and 61 not separately argued, for the
reasons provided by the Examiner and above.
Rejections 117 & III
Figure 22 from Appellant's Specification illustrates the claimed
subject matter of independent claims 33 and 51----each included in Rejection
II-and is copied below:
340
~ 356
268 252 254
-2.fill 348
,;r--1~~~~~-/-.......1..:--~~..!71}~ ~~ ............... )~342
262 276
280 280
FIG. 22
7 In Rejection II, the Examiner additionally rejects claims 58, 59, and 61-
addressed above in our discussion of Rejection I-by relying on the same
Konishi and Quek references cited in Rejection I, along with Sekiguchi.
Because we have sustained the rejection of claims 58, 59, and 61 based on
Konishi and Quek alone, we need not determine whether these claims are
also obvious in view of Konishi, Quek and Sekiguchi. See In re Hyon, 679
F.3d 1363, 1367 (Fed. Cir. 2012) (the affirmance of an obviousness rejection
of certain claims under§ 103(a) made it unnecessary to reach other grounds
of rejection including those claims). We, therefore, confine our discussion
here to independent claims 33 and 51, and any separately argued claims.
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Application 13/944,825
Figure 22 "illustrates two-level stepped interposer with openings for
stacking three semiconductor die." Spec. ,r 15.
Claim 51 is illustrative of the subject matter encompassed by
Rejections II and III, and is copied below from the Claims Appendix to the
Appeal Brief, with a key limitation italicized:
51. A method of making a semiconductor device, comprising:
providing a stepped substrate [342] including a first
surface, a first step level opposite the first surface, and a second
step level extending up from the first step level;
disposing a first semiconductor die [252] in contact with
the first step level with a bump [256] formed on an active surface
of the first semiconductor die contacting a first conductive via
[344] formed through the stepped substrate while maintaining
separation between the first semiconductor die and the stepped
substrate at the second step level;
disposing a second semiconductor die [350] in contact
with the second step level and the first semiconductor die with a
bump [356] formed on an active surface of the second
semiconductor die contacting a second conductive via [346]
formed through the stepped substrate;
forming a first interconnect structure [274] over the first
surface of the stepped substrate; and
depositing an encapsulant [358] over the second
semiconductor die, first step level, second step level, and in the
separation between the first semiconductor die and the stepped
substrate.
Br. 29 ( emphasis added, reference numbers inserted).
Regarding claim 51, the Examiner finds that Quek discloses the
recited method, except for the steps requiring the formation of a first
interconnect structure and the deposition of an encapsulant over the second
semiconductor die and other recited components. Final Act. 7-8. The
Examiner relies on Konishi and Sekiguchi to address these missing steps.
Id. at 8. Specifically, the Examiner finds that Konishi discloses the
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Application 13/944,825
deposition of an encapsulant over a semiconductor die, a first and second
step level, and in the separation between the die and the stepped substrate.
Id. The Examiner finds further that Sekiguchi teaches formation of an
interconnect structure. Id. Based on this disclosure, the Examiner concludes
that it would have been obvious to modify Quek' s device to include
Sekiguchi' s interconnect structure "in order to provide electrical connection
to the device," and to deposit an encapsulant over the semiconductor die "in
order to provide better protection to the device." Id.
The Examiner makes similar findings and conclusions regarding claim
33. Final Act 5-7. Independent claim 33 recites a method similar to claim
51, but requires disposing the first semiconductor die 260 in an opening
through the stepped substrate prior to the deposition of (now "second" and
"third") semiconductor dies 252 and 350, respectively. Br. 3--4, 27.
Additionally, in claim 33, the encapsulant is deposited over the third
semiconductor die 350, the first and second step levels, "and in the
separation between the second semiconductor die and the stepped substrate."
Br. 28.
We address the claims encompassed by Rejections II and III
separately to the extent they are so argued by Appellant.
Claim 51
Regarding claim 51, Appellant argues that, contrary to the Examiner's
findings, Quek does not disclose the second semiconductor die "in contact
with" the second step level and first semiconductor die. Br. 17.
This argument fails to persuade us of reversible error. As correctly
noted by the Examiner (Ans. 16-17), claim 51 does not specifically recite
the contact must be "direct" contact. Appellant has not directed us to any
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Application 13/944,825
definition of the term "contact" so as to distinguish mechanical, thermal,
and/ or electrical contact between these components as disclosed in Quek.
See e.g., Quek 6:4---6. Moreover, Appellant fails to challenge the Examiner's
position that Quek's components are in such "contact." Ans. 16-17.
Appellant contends further that it would not have been obvious to
modify Quek with the steps that the Examiner acknowledges are missing
therefrom--i.e., the formation of the interconnect structure and the
deposition of encapsulant-to arrive at the present claims, because the
structure resulting from the inclusion of such steps in Quek' s process would
be "technically duplicative, if not incompatible, with" Quek's existing
features. Br. 17-19.
We disagree with Appellant's argument for the well-stated reasons
provided by the Examiner, uncontested by Appellant, which we adopt as our
own. Ans. 18, 9-13.
Claims 53 & 60
Claim 53 is dependent from claim 51 and requires the additional steps
of "providing an opening through the stepped substrate extending from the
first step level to the first surface" and also "disposing a third semiconductor
die in the opening of the stepped substrate." Br. 30. Claim 60, dependent
from claim 5 8, recites similar limitations and presents similar issues on
appeal. Thus, we consider these claims together. The Examiner relies on
Quek's disclosure for teaching each of the steps recited in claims 53 and 60.
Final Act. 9, 11.
Regarding claim 53, Appellant asserts that Quek does not teach these
steps because Quek' s semiconductor die 10--the element the Examiner
maps to the recited "third semiconductor die"-"is not disposed in the
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Application 13/944,825
opening of the stepped substrate, i.e., the opening through the stepped
substrate extending from the first step level to the first surface. Br. 19--20.
Similarly, Appellant argues that claim 60's limitations are not satisfied by
Quek because Quek's element "10 is not disposed in the opening of the first
substrate." Id. 24--25.
This line of argument is not persuasive. In the Answer (Ans. 14--15),8
the Examiner provides annotated versions of Quek's Figures 1 and 3, set
forth below, supporting the finding that these limitations are taught:
FIG. 3
21.
' ·:,2 !--~
'-----t'Hi-.l1~~~~:::t:::~~-n....w......u...u~-l' 19
,.
!
17
F JG. 1
8 This portion of the Answer is directly responsive to Appellant's arguments
regarding a similar limitation appearing in claim 33. The Examiner adopts
the same reasoning for claims 53 and 60 (Ans. 19--20), so it applies with
equal force here.
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Application 13/944,825
Quek's Figures 1 and 3, as annotated by the Examiner, identify the
opening, the first step level, and first surface of Quek's device. We discern
no error in the Examiner's interpretation of Quek's Figures. Furthermore,
Appellant makes no reply to the Examiner's explanation as provided in the
Answer, and thus fails to identify error in the rejection of claims 53 and 60.
Claim 33
For this claim, Appellant makes substantially the same arguments as
those made for other claims, e.g., 51, 53, 58, and 60. Br. 12-17. Namely,
Appellant outlines contentions regarding the recited "opening" (Br. 12-13)
and the claimed "contact" between the second and third semiconductor dies
(id. 13-14), and repeats assertions regarding the incompatibility of Konishi's
sealant and Sekiguchi's interconnect substrate (id. 14--16).
We have already addressed these arguments, supra, and have found
them unpersuasive of reversible error.
In sum, because Appellant fails to identify error in Rejections II and
III, we sustain these rejections for the reasons provided by the Examiner and
above.
DECISION
The Examiner's final decision to reject claims 33 and 46-64 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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