Ex Parte Pagaila et alDownload PDFPatent Trial and Appeal BoardJul 13, 201712714190 (P.T.A.B. Jul. 13, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/714,190 02/26/2010 Reza A. Pagaila 2515.0230 CIP 6196 112165 7590 07/17/2017 STATS ThmPAr/PATFNT T AW (TROUP- EXAMINER Atkins and Associates, P.C. 55 N. Arizona Place, Suite 104 NADAV, ORI Chandler, AZ 85225 ART UNIT PAPER NUMBER 2811 NOTIFICATION DATE DELIVERY MODE 07/17/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): main@plgaz.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte REZA A. PAGAILA, YAOJIAN LIN, JUN MO KOO, and HEEJO CHI Appeal 2016-005777 Application 12/714,19c1 Technology Center 2800 Before ADRIENE LEPIANE HANLON, DONNA M. PRAISS, and MERRELL C. CASHION, JR., Administrative Patent Judges. PRAISS, Administrative Patent Judge. DECISION ON APPEAL2 Appellants appeal under 35 U.S.C. § 134 the final rejection of claims 1—19, 27—29, and 31—43. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). We AFFIRM-IN-PART. 1 The real party in interest is identified as STATS ChipPAC, Ltd. App. App. Br. 1. 2 In this Opinion, we refer to the Specification filed Feb. 26, 2010 (“Spec.”), the Final Office Action dated July 2, 2015 (“Final Act.”), the Appeal Brief filed Dec. 1, 2015 (“App. Br.”), the Examiner’s Answer dated Mar. 16, 2016 (“Ans.”), and the Reply Brief filed May 16, 2016 (“Reply Br.”). Appeal 2016-005777 Application 12/714,190 Appellants’ invention is said to be directed to “semiconductor devices and, more particularly, to a semiconductor device and method of forming an interposer with an open cavity to contain a semiconductor die in a wafer level chip scale package.” Spec. 12. Claim 1 is illustrative (disputed terms italicized): 1. A method of making a semiconductor device, comprising: providing a first interposer including an opening and a vertical conduction path through the first interposer; disposing a first semiconductor die over a first surface of the first interposer, an active surface of the first semiconductor die oriented toward the first interposer; disposing a second semiconductor die within the opening of the first interposer, a non-active surface of the second semiconductor die oriented toward the first semiconductor die; depositing an encapsulant over the first semiconductor die and around the second semiconductor die within the opening of the first interposer; and forming an interconnect structure over the first interposer, the encapsulant, and the second semiconductor die by, (a) forming an insulating layer on a surface of the encapsulant, on an active surface of the second semiconductor die opposite the non-active surface, and on a second surface of the first interposer opposite the first surface, and (b) forming a conductive layer on the active surface of the second semiconductor die and on the second surf ace of the first interposer. App. Br. 38—39 (Claims App’x). The following rejections are maintained by the Examiner (Ans. 2—15) and appealed by Appellants (App. Br. 7—36): 2 Appeal 2016-005777 Application 12/714,190 1. Claims 8, 11, 14, 17, and 31—42 stand rejected as anticipated or obvious over Jiang;3 2. Claims 9, 10, 13, 15, 16, and 19 stand rejected as obvious over Jiang alone or in combination with secondary references; 3. Claims 1, 5, and 27—29 stand rejected as obvious over Shimada4 in view of Sekiguchi;5 and 4. Claims 2—4, 6, 7, and 43 stand rejected as obvious over Shimada and Sekiguchi in combination with secondary references. ISSUES The dispositive issues on appeal are whether the Examiner erred in determining that (1) a mounting board formed on the entire structure of Shimada’s Figure 3 means that the insulating and conductive layers of the mounting board are formed on the active surface of the second semiconductor die as required by independent claim 1 and (2) Jiang’s Figure 5 discloses an interconnect structure including an insulating layer and a conductive layer over or “above in place or position” the surfaces recited in independent claims 8, 14, and 38. OPINION Appellants do not separately argue the patentability of claims 11, 17, 31—36, and 39-42 under 35 U.S.C. § 102(b) as anticipated by Jiang in this appeal. App. Br. 29-36. In accordance with 37 C.F.R. § 41.37(c)(l)(iv), 3 Jiang et al., US 6,906,415 B2, issued June 14, 2005 (“Jiang”). 4 US 6,365,963 Bl, issued Apr. 2, 2002. 5 US 2008/0128881 Al, published June 5, 2008. 3 Appeal 2016-005777 Application 12/714,190 claims 11 and 31—33 stand or fall together with claim 8, claims 17 and 34— 36 will stand or fall together with claim 14, and claims 39-42 will stand or fall together with claim 38. Appellants also do not separately argue the patentability of claims 9— 13, 15—19, 31—37, and 39-42 as unpatentable under 35 U.S.C. § 103(a) over Jiang alone or together with additional references in this appeal. Id. at 18— 28. In accordance with 37 C.F.R. § 41.37(c)(l)(iv), and based upon the lack of arguments directed to the subsidiary rejections, claims 9—13 and 31—33 stand or fall together with claim 8, claims 15—19 and 34—37 will stand or fall together with claim 14, and claims 39-42 will stand or fall together with claim 38. Similarly, Appellants do not separately argue the patentability of claims 2—7, 27—29, and 43 as unpatentable under 35 U.S.C. § 103(a) over Shimada in view of Sekiguchi in this appeal.6 App. Br. 8—17. In accordance with 37 C.F.R. § 41.37(c)(l)(iv), and based upon the lack of arguments directed to the subsidiary rejections, claims 2—7, 27—29, and 43 stand or fall together with claim 1. Claim 1: Obviousness over Shimada and Sekiguchi Regarding claim 1, the Examiner finds that Shimada’s Figure 3 discloses the claimed method of making a semiconductor device with the 6 Although Appellants argue the patentability of claim 43 over Jiang as a reference (App. Br. 17—18), the Examiner notes that the rejection of claim 43 over Jiang was a typographical error because claim 43 depends from claim 1 and claim 1 does not stand rejected over Jiang (Ans. 23). Thus, Appellants do not separately argue the Examiner’s rejection of claim 43 over Shimada together with additional references (Final Act. 14). 4 Appeal 2016-005777 Application 12/714,190 exception of forming an interconnect structure as required by claim 1, however, Shimada discloses forming a mounting board on solder balls in Figures 3 and 4. Final Act. 11—12. The Examiner also finds that Sekiguchi teaches in Figure 1 forming an encapsulant over the first semiconductor die and forming the interconnect structure under the first interposer, the encapsulant, and the second semiconductor die as required by claim 1. Id. at 12. The Examiner determines that it would have been obvious for a person having ordinary skill to modify Shimada’s semiconductor by forming the encapsulant and interconnect structure taught by Sekiguchi in order to provide better protection to the die and in order to provide external connections to the device. Id. at 12—13. Appellants challenge the rejection of claim 1 by arguing that Shimada does not teach the interconnect structure required by claim 1 and that Shimada’s solder balls do not meet the limitations of the interconnect structure. App. Br. 9-10. Appellants also argue that Sekiguchi does not disclose the interconnect structure as claimed because the Final Rejection “does not identify any features in Sekiguchi that shows the first and second semiconductor die” therefore Sekiguchi “cannot disclose an interconnect structure formed on surfaces of such features that are missing from Sekiguchi.” Id. at 11—13. Appellants further argue that in order to apply Sekiguchi’s mounting board over the surface of the rigid board opposite the second chip in Shimada, Shimada’s base film would have to be removed and the solder balls would have to be placed on the rigid board, however, according to Appellants, Shimada teaches away from doing so in order to produce a semiconductor device with a smaller thickness. Id. at 15—16. 5 Appeal 2016-005777 Application 12/714,190 The Examiner responds that claim 1 requires that the interconnect structure is “over the first interposer . . and not as Appellants’ arguments suggest “over and in direct contact with surfaces of’ the interposer, the encapsulant, and the second semiconductor die. Ans. 17. Similarly, the Examiner finds that the broadest reasonable interpretation of “on” as in “forming an insulating layer on a surface of the encapsulant...” and “forming a conductive layer on the active surface of the second semiconductor die . . .” recited in claim 1, does not require a structure wherein the one recited element is “over and in direct contact” with the second recited element. Id. at 17—18. The Examiner further finds that placing a mounting board on top of solder balls 13 in Shimada’s Figure 3 cures the deficiencies of the depicted structure because the mounting board is disposed on the solder balls. Id. at 18 (quoting Shimada 3:54—56). The Examiner’s annotated and modified Figure 3 from Shimada is shown below: msn-scfcfv© swrfaos 111 110 21 11 113 112 104 Annotated and modified Figure 3 of Shimada shows a mounting board disposed on top of the solder balls 13. The Examiner finds that the mounting board is formed on the entire structure of Shimada’s Figure 3 because solder balls 13 are integral to Shimada’s structure. Id. at 19. 6 Appeal 2016-005777 Application 12/714,190 Because the mounting board is formed on the entire structure, it is also formed on the active surface of the second semiconductor die, on the non active surface of the second semiconductor die, on a second surface of the first imposer, and on the first surface of the first interposer as required by the claim. Id. The Examiner further responds that mounting boards are known in the art to be interconnect structures because they include conductive layers to provide external connections and at least one insulating layer to insulate the conductive layers from each other. Id. The Examiner finds that Sekiguchi evidences that mounting boards include conductive layers for external connections to the device and at least one insulating layer to insulate the conductive layers. Id. (citing Sekiguchi Fig. 1). In the Reply Brief, Appellants argue that the Examiner’s interpretation of claim 1 as encompassing an interconnect structure formed on solder balls 13 in Shamada’s Figure 3 renders superfluous the limitations of “forming an insulating layer on a surface of the encapsulant, on an active surface of the second semiconductor die opposite the non-active surface, and on a second surface of the first interposer opposite the first surface.” Reply Br. 4. Appellants assert that such an interpretation would be unreasonable. Id. at 4-5. Appellants do not dispute the Examiner’s finding that Shimada discloses first and second semiconductor dies as well as an interposer such that the second semiconductor die is within an opening of the interposer as required by claim 1 (Final Act. 11). Appellants also do not dispute the Examiner’s finding that it is well known in the art that mounting boards, such as those disclosed in Shimada and Sekiguchi, are interconnect 7 Appeal 2016-005777 Application 12/714,190 structures that include conductive layers and at least one insulating layer to insulate the conductive layers from each other (Ans. 19). The issue before us is whether claim 1 requires that the interconnect structure be formed in a manner proposed by the Examiner based on the combination of Shimada and Sekiguchi. After considering the arguments and evidence presented by the Examiner and Appellants, we find that Appellants’ arguments are supported by the preponderance of the evidence for the reasons discussed below. We agree with the Examiner that the term “over” as recited in claim 1 does not require direct contact. In addition, as discussed infra, Appellants do not dispute the Examiner’s definition of “over” as meaning “above in place or position” (Ans. 26, citing Dictionary.com). However, we agree with Appellants (App. Br. 12; Reply Br. 4) that it would be unreasonable to interpret claim 1 such that a mounting board formed on the entire structure of Shimada means the mounting board is formed both “over . . . the second semiconductor die” and “on an active surface of the second semiconductor die opposite the non-active surface” as recited in claim 1. That would ascribe the same definition to the term “on” as the term “over” in the claim. Consistent with Appellants’ arguments, the dictionary definition of “on” embraces a support, attachment, covering, and connection relationship between two things.7 Accordingly, we find that “on” as used in claim 1 means “directly connected to.” Based on the correct claim construction, we find that annotated Figure 3 of Shimada above, in which the mounting board 7 Dictionary.com, which the Examiner relies upon for the definition of “over,” provides the following definitions for the word “on”: (1) “so as to be or remain supported by or suspended from”; (2) “so as to be attached to or unified with”; (3) “so as to be a covering or wrapping for”; and (4) “in connection, association, or cooperation with; as a part or element of’. 8 Appeal 2016-005777 Application 12/714,190 is disposed on top of the solder balls, shows forming an interconnect structure over the first interposer, the encapsulant, and the second semiconductor die as required by claim 1, but does not show forming the insulating layer of the interconnect “on an active surface of the second semiconductor die opposite the non-active surface” as recited in claim 1. Because the Examiner’s rejection is based on a claim construction of claim 1 that does not require the insulating layer and the conductive layer of the interconnect structure to be directly connected to an active surface of the second semiconductor die, the Examiner reversibly erred in rejecting claim 1 over the combination of Shimada and Sekiguchi. The Examiner’s finding regarding the location of Sekiguchi’s interconnect structure being “under the first interposer, the encapsulant, and the second semiconductor die” in Sekiguchi’s device (Final Act. 12) does not adequately explain why it would have been obvious to form an interconnect structure with an insulating layer of the interconnect on an active surface of the second semiconductor die of Shimada. As noted by Appellants, Shimada’s device includes a base insulator film 110, which Appellants assert “would have to be removed” if a skilled artisan modified Shimada’s device with Sekiguchi’s mounting board “[i]n order to apply mounting board 40 from Sekiguchi over the surface of the rigid board 101 opposite second chip 12 in Shimada.” App. Br. 15. The Examiner does not adequately explain why it would have been obvious to replace Shimada’s base insulator film 110 with Sekiguchi’s mounting board 40 in response to Appellants’ argument. Therefore, based on the record cited in this appeal, we reverse the Examiner’s rejection of claim 1 over the combination of Shimada and Sekiguchi. 9 Appeal 2016-005777 Application 12/714,190 We also reverse the rejections of claims 2—7, 27—29, and 43, which each depend from claim 1, because they do not cure the deficiencies of the combination of Shimada and Sekiguchi discussed above. Claim 8: Anticipation or Obviousness over Jiang Regarding claim 8, the Examiner finds that Jiang discloses a semiconductor device having an interposer, a first semiconductor die over the interposer, a second semiconductor die within an opening of the interposer, an encapsulant around the first semiconductor die, the second semiconductor die, and within the opening of the interposer, and the interconnect structure required by claim 8. Final Act. 5 (citing Jiang Fig. 3, items 61, 40, 20, 61 A). The Examiner further finds that Jiang “do[es] not explicitly state that the interconnect structure is formed over the second semiconductor die and surface of the interposer[,]” however, it would have been obvious to a skilled artisan “to turn over the device such that the interconnect structure is formed over a surface of the second semiconductor die, over a surface of the encapsulant, and over a second surface of the interposer ... in order to simplify the processing steps of making the device.” Id. at 6. Appellants challenge both the anticipation and obviousness rejections of claim 8 by arguing that Jiang fails to teach each limitation of claim 8, specifically, “the features of the top interposer 61A over upper surface 66 of interposer 61 ... are not also over lower surface 68 of interposer 61.” App. Br. 19, 30. Appellants also argue that the obviousness rejection of claim 8 is in error because Jiang does not disclose “that interposer 61A is formed over a surface of interposer 61 opposite to the surface over which semiconductor 10 Appeal 2016-005777 Application 12/714,190 device 40 is disposed.” Id. at 19. According to Appellants, Jiang does not disclose a step of forming a build-up interconnect structure over a surface of lower package 110 because “upper package 110’ is completely formed prior to mounting to lower package” and “interposers 61 are simultaneously formed in the format of a substrate sheet or strip 62.” Id. at 19—20 (citing Jiang 8:38-40). Appellants also argue that the Examiner’s finding that it would have been obvious to form a build-up interconnect structure over the claimed surfaces is “taking Official Notice [of] forming a build-up interconnect structure over the second semiconductor die and a surface of the interposer opposite the first semiconductor die” that is not supported by evidence. Id. at 20-21. The Examiner responds that “Appellants admit that interposer 61A is formed over upper surface 66 of interposer 61.” Ans. 26. The Examiner finds that “over” means “above in place or position” and is not synonymous with “directly over.” Id. at 26, 29. According to the Examiner, that means “that interposer 61A is also formed over or above lower surface 68 of interposer 61” {id. (citing dictionary.com)) and claim 8 “does not require that each of the recited elements of the built-up interconnect structure must be formed directly over the claimed surfaces” (id. at 29). Referring to annotated Figure 5 of Jiang, the Examiner further finds that “if upper package 110’ is mounted over the same surface of interposer 61, then said upper package 110’ is also formed over a second surface of the interposer 61 opposite the first surface.” Id. at 27 (emphasis omitted). Annotated Figure 5 is shown below: 11 Appeal 2016-005777 Application 12/714,190 Stereo?* nscfc structure Annotated Figure 5 shows a stacked package of two multidie semiconductor device packages. Jiang 6:60—62. The Examiner finds that claim 8 does not require the insulating layer be formed before the conductive layer over the claimed surfaces, but, rather, merely that a build-up interconnect structure include an insulating layer and a conductive layer wherein each is formed over the claimed surfaces. Ans. 28. It is the Examiner’s position that the completed build-up interconnect structure meets the recitations of claim 8. Id. The Examiner also responds that it is well known in the art that a carrier substrate is a circuit board and that “a circuit board is an interconnect structure since it comprises insulating layers and conductive layers providing interconnections between the various elements of the package.” Id. at 30. The Examiner finds that Jiang teaches forming an interconnect structure 8 under the package and supports the Examiner’s position that it is well known in the art to turn the package upside down in order to form the interconnect structure over the package. Id. at 30-31 (annotating Jiang Fig. 1). In the Reply Brief, Appellants argue that the Examiner’s interpretation of claim 8 requiring any interconnect structure that includes an insulating 12 Appeal 2016-005777 Application 12/714,190 layer and a conductive layer renders superfluous “the limitation forming a build-up interconnect structure over a second surface of the interposer opposite the first surface.” Reply Br. 6; see id. at 11 (adopting arguments against obviousness rejections for the anticipation rejection of claim 8 over Jiang). We are not persuaded by Appellants’ arguments because claim 8 does not require any particular order of forming the insulating layer and the conductive layer of the build-up interconnect structure, therefore completely forming a build-up interconnect structure meets the required step of forming a build-up interconnect structure. In addition, the Examiner’s interpretation is consistent with the Specification which states “[a] build-up interconnect structure 274 is formed over semiconductor die 260 and interposer 244. The build-up interconnect structure 274 includes an insulating or passivation layer . . . .” Spec. 1 66. Thus the Specification does not require a particular sequence of process steps for forming a build-up interconnect structure having an insulating layer and a conductive layer. In addition, Appellants do not dispute the Examiner’s interpretation of the term “over” as being “above in place or position” (Ans. 26). The Examiner’s definition is consistent with the Specification which does not define “over” as meaning directly over. In the absence of reversible error by the Examiner regarding Jiang’s disclosures being shown by Appellants, we affirm the Examiner’s rejection of claim 8 as anticipated by Jiang. 8 We need not address separately the 8 We note that affirmance under Section 102 as anticipated by Jiang is justified in view of (1) the construction of the term “over” to mean “above in place or position” as well as (2) the failure to specifically recite in the claim steps for forming an interconnect structure distinct from merely placing the interconnect over the interposer, etc. as disclosed in Jiang’s Figure 5. 13 Appeal 2016-005777 Application 12/714,190 Examiner’s rejection of claim 8 under 35 U.S.C. § 103(a) because anticipation is the epitome of obviousness. See In re Pearson, 494 F.2d 1399, 1402 (CCPA 1974); In re Fracalossi, 681 F.2d 792, 794 (CCPA 1982). In addition to the rejections of claim 8, we also affirm the rejections of its dependent claims 9—13 and 31—33. Claim 14: Anticipation or Obviousness over Jiang Regarding claim 14, the Examiner finds that Jiang discloses a semiconductor device having an interposer, a second semiconductor die within an opening of the interposer, a first semiconductor die over the interposer and second semiconductor die, and the interconnect structure including bump material between the first semiconductor die and the interposer as required by claim 14. Final Act. 4—5 (citing Jiang Fig. 5, items 20, 40, 56, 61, 61A, 90, Fig. 9). The Examiner further finds that Jiang “do[es] not explicitly state forming the interconnect structure over the interposer, the encapsulant, and the second semiconductor die[,]” however, it would have been obvious to a skilled artisan “to turn over the device such that the interconnect structure is formed over the second semiconductor die and surface of the interposer ... in order to simplify the processing steps of making the device.” Id. at 5. Appellants challenge both the anticipation and obviousness rejections of claim 14 by arguing that Jiang fails to teach each limitation of claim 14, specifically, “the features of the top interposer 61A over upper surface 66 of interposer 61 ... are not also over lower surface 68 of interposer 61. Therefore, top interposer 61A fails to teach the limitation of the interconnect structure over the surfaces according to claim 14.” App. Br. 22, 32—33. 14 Appeal 2016-005777 Application 12/714,190 Appellants also argue that the anticipation rejection of claim 14 is in error because Jiang does not disclose that interposer 61A is “formed over a surface of interposer 61 opposite to the surface over which second-level semiconductor device 40 is disposed.” Id. at 34. According to Appellants, Jiang does not disclose a step of forming a build-up interconnect structure over a surface of lower package 110 because “[ujpper package 110’ is completely formed prior to mounting to lower package” and “interposers 61 are simultaneously formed in the format of a substrate sheet or strip 62.” Id. at 33 (citing Jiang 8:38—40). Appellants also argue that the Examiner’s finding that it would have been obvious to form a build-up interconnect structure over the claimed surfaces is “taking Official Notice [of] forming a build-up interconnect structure over the second semiconductor die and a surface of the interposer opposite the first semiconductor die” that is not supported by evidence. Id. at 24. The Examiner responds that Appellants’ arguments are the same as those presented with respect to claim 8, that claim 14 is broader than claim 8, and that the same response regarding claim 8 applies to claim 14 as well. Ans. 32. The Examiner further finds that the step of forming an interconnect structure recited in claim 14 does not recite any elements associated with the interconnect structure. Id. Therefore Jiang’s interconnect structure 110’, which is pre-assembled prior to being formed over packaging structure 110, teaches the interconnect structure required by claim 14 because it is over a surface of the interposer 61 opposite the first semiconductor die 40 and over a surface of the encapsulant 90 and the second semiconductor 20. Id. at 32— 33 (citing Jiang Figs. 4, 5). 15 Appeal 2016-005777 Application 12/714,190 In the Reply Brief, Appellants argue that the Examiner’s interpretation of claim 14 is not reasonable because it only requires “an interconnect structure formed over either surface of the interposer . . . rendering the limitation over a surface of the interposer opposite the first semiconductor die superfluous.” Reply Br. 7. We are not persuaded by Appellants’ arguments because claim 14 does not require any particular method steps for forming the interconnect structure over surfaces of the interposer, encapsulant, and second semiconductor die. Therefore, a completely formed interconnect structure meets the required step of forming an interconnect structure. In addition, the Examiner’s interpretation is consistent with the Specification which states “[a] build-up interconnect structure 274 is formed over semiconductor die 260 and interposer 244. The build-up interconnect structure 274 includes an insulating or passivation layer . . . .” Spec. 1 66. Thus the Specification does not require a particular sequence of process steps for forming an interconnect structure. In addition, Appellants do not dispute the Examiner’s interpretation of the term “over” as being “above in place or position” (Ans. 26). The Examiner’s definition is consistent with the Specification which does not define “over” as meaning directly over. In the absence of reversible error by the Examiner being shown by Appellants, we affirm the Examiner’s rejection of claim 14 as well as its dependent claims 17 and 34—36 as anticipated by Jiang.9 We need not address separately the Examiner’s rejection of claim 14 under 35 U.S.C. § 103(a) because anticipation is the epitome of obviousness. See Pearson, 494 F.2d at 1402; Fracalossi, 681 F.2d at 794. 9 See footnote 8, supra. 16 Appeal 2016-005777 Application 12/714,190 Claim 38: Anticipation or Obviousness over Jiang Regarding claim 38, the Examiner finds that Jiang discloses a semiconductor device having an interposer, a second semiconductor die within an opening of the interposer, a first semiconductor die over the interposer and second semiconductor die, and an interconnect structure including an insulating layer formed over the interposer and the second semiconductor die and bump material over the interconnect structure and between the first semiconductor die and the interposer as required by the claim. Final Act. 2—3 (citing Jiang Fig. 5, items 20, 40, 56, 61, 61 A, Fig. 9). The Examiner further finds that Jiang “do[es] not explicitly state that the interconnect structure is formed over the second semiconductor die and surface of the interposer[,]” however, it would have been obvious to a skilled artisan “to turn over the device such that the interconnect structure is formed over the second semiconductor die and surface of the interposer . . . in order to simplify the processing steps of making the device.” Id. at 3. Appellants challenge the rejections of claim 38 by arguing that Jiang fails to teach each limitation of claim 38, specifically, “the features of the top interposer 61A over upper surface 66 of interposer 61 ... are not also over lower surface 68 of interposer 61. Therefore, top interposer 61A fails to teach the limitation of the interconnect structure over the surfaces according to claim 14.” App. Br. 25, 35. Appellants also argue that the anticipation rejection of claim 38 is in error because Jiang does not disclose that interposer 61A is “formed over a surface of interposer 61 opposite to the surface over which second-level semiconductor device 40 is disposed.” Id. at 35, 36. According to Appellants, Jiang does not disclose a step of forming a build-up interconnect structure over a semiconductor die and a surface of 17 Appeal 2016-005777 Application 12/714,190 an interposer because “[u]pper package 110’ is completely formed prior to mounting to lower package[,]” “interposers 61 are simultaneously formed in the format of a substrate sheet or strip 62[,]” and “upper package 110’ is mounted over the same surface of interposer 61 as second-level semiconductor device 40, such that upper package 110’ is not formed over a second surface of the interposer 61 opposite the first surface.” Id. at 35—36 (citing Jiang 8:38-40). Appellants also argue that the Examiner’s finding that it would have been obvious to form a build-up interconnect structure over the claimed surfaces is “taking Official Notice [of] forming a build-up interconnect structure over the second semiconductor die and a surface of the interposer opposite the first semiconductor die” that is not supported by evidence. Id. at 27. The Examiner responds that Appellants’ arguments are the same as those presented with respect to claim 8, that claim 38 is broader than claim 8, and that the same response regarding claim 8 applies to claim 38 as well. Ans. 32. The Examiner further finds that the step of forming an interconnect structure recited in claim 38 does not recite any elements associated with the interconnect structure. Id. Therefore Jiang’s interconnect structure 110’, which is pre-assembled prior to being formed over packaging structure 110, teaches the interconnect structure required by claim 38 because it is formed over the second semiconductor die 20 and a surface of the interposer 61 opposite the first semiconductor die 40. Id. at 32—33 (citing Jiang Figs. 4, 5). In the Reply Brief, Appellants argue that the Examiner’s interpretation of claim 38 is not reasonable because it only requires “any interconnect structure including an insulating layer and a conductive layer . . . merely 18 Appeal 2016-005777 Application 12/714,190 disposed over . . . either surface of the interposer . . . rendering the limitation forming a build-up interconnect structure over the second semiconductor die and a surface of the interposer opposite the first semiconductor die superfluous.” Reply Br. 9. We are not persuaded by Appellants’ arguments because claim 38 does not require any particular method steps for forming the interconnect structure over surfaces of the interposer and first and second semiconductor dies. Therefore, a completely formed interconnect structure meets the required step of forming an interconnect structure. In addition, the Examiner’s interpretation is consistent with the Specification which states “[a] build-up interconnect structure 274 is formed over semiconductor die 260 and interposer 244. The build-up interconnect structure 274 includes an insulating or passivation layer . . . .” Spec. 1 66. Thus the Specification does not require a particular sequence of process steps for forming an interconnect structure. In addition, Appellants do not dispute the Examiner’s interpretation of the term “over” as being “above in place or position” (Ans. 26). The Examiner’s definition is consistent with the Specification which does not define “over” as meaning directly over. In the absence of reversible error by the Examiner being shown by Appellants, we affirm the Examiner’s rejection of claim 38 as well as its dependent claims 39-42 as anticipated by Jiang.10 We need not address separately the Examiner’s rejection of claim 38 under 35 U.S.C. § 103(a) because anticipation is the epitome of obviousness. See Pearson, 494 F.2d at 1402; Fracalossi, 681 F.2d at 794. 10 See footnote 8, supra. 19 Appeal 2016-005777 Application 12/714,190 DECISION The Examiner’s decision rejecting claims 1—7, 27—29, and 43 as unpatentable under 35 U.S.C. § 103(a) over Shimada and Sekiguchi and other references is reversed. The Examiner’s decision rejecting claims 8—19 and 31—42 under 35 U.S.C. §§ 102(b) and 103(a) as anticipated by or obvious over Jiang and other references is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136. ORDER AFFIRMED-IN-PART 20 Copy with citationCopy as parenthetical citation