Ex Parte Pagaila et al

Patent Trial and Appeal Board

Jun 20, 2016

12766607 (P.T.A.B. Jun. 20, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121766,607 04/23/2010
112165 7590 06/22/2016
STATS ChipPAC/PATENTLAWGROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
Reza A. Pagaila
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0213 1824
EXAMINER
JIANG, FANG-XING
ART UNIT PAPER NUMBER
2815
NOTIFICATION DATE DELIVERY MODE
06/22/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte REZA A. P AGAILA and Y AOJIAN LIN
Appeal2015-000023
Application 12/766,607
Technology Center 2800
Before JOHNNY A. KUMAR, LINZY T. McCARTNEY, and
SCOTT B. HOWARD, Administrative Patent Judges.
HOW ARD, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-3, 5, 6, 13-16, 18-28, 35, and 36. Claims 3, 4, 7, 10 and 17 are
objected to as being dependent upon a rejected base claim and claims 8-14
and 29-34 are allowed.2 Ans. 2. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We affirm-in-part.
1 Appellants identify ST ATS ChipP AC, Ltd. as the real party in interest.
App. Br. 1.
2 We note claim 3 is identified as both rejected and objected to, claim 10 is
identified as being both allowed and objected to, claims 13, 14, 33, and 34
are identified as being both allowed and rejected, and claim 26 is neither
rejected nor identified as allowed. See Final Act. 18, 24--26; Ans. 2. We
leave it to the Examiner to resolve the inconsistency.
Appeal2015-000023
Application 12/766,607
THE INVENTION
The claimed invention is directed to a semiconductor device and
method of forming openings in thermally-conductive frame of fan-out wafer
level chip scale packages (FO-WLCSP) to dissipate heat and reduce package
height. Abstract; Spec. ,-r 1.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method of making a semiconductor device, comprising:
providing a thermally-conductive frame;
forming an interconnect structure over a first surface of the
thermally-conductive frame, the interconnect structure including
an electrical interconnect path and thermal conduction path;
mounting a first semiconductor die to the electrical
interconnect path and thermal conduction path of the
interconnect structure over the first surface of the thermally-
conductive frame with a portion of the electrical interconnect
path and a portion of the thermal conduction path each vertically
aligned between a footprint of the first semiconductor die and the
thermally-conductive frame;
removing a portion of a back surface of the first
semiconductor die;
forming an opening in the thermally-conductive frame
extending to the electrical interconnect path of the interconnect
structure; and
mounting a second semiconductor die over a second surf
ace of the thermally-conductive frame opposite the first surface
of the thermally-conductive frame with the second
semiconductor die electrically connected to the interconnect
structure using a first bump disposed in the opening of the
thermally-conductive frame.
2
Appeal2015-000023
Application 12/766,607
REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
W oinarowski us 5,324,687 June 28, 1994
Hsieh US 2004/0150977 Al Aug. 5, 2004
Mallik US 2005/0121764 Al June 9, 2005
Liu US 2006/0125113 Al June 15, 2006
Chow US 2009/0236733 Al Sept. 24, 2009
REJECTIONS3
Claims 15, 16, and 21 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Chow. Final Act. 15-17.
Claims 1-3, 18, 22, 23, 27, 28, and 33-36 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Chow in view ofWojnarowski
and Liu.4 Final Act. 18-24.
Claims 5, 14, 19, and 25 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Chow in view of Wojnarowski, Liu, and ivfallik.
Final Act. 24--25.
Claims 6, 13, 20, and 24 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Chow in view of W ojnarowski, Liu, and Hsieh.
Final Act. 25-26
3 In the Answer, the Examiner withdrew the rejection of claims 3-34 under
35 U.S.C. § 112, second paragraph and claims 6, 8, 13, 20, 21, 24, and 27
under 35 U.S.C. § 112, first paragraph.
4 Liu is incorrectly identified as Lin in parts of the Final Action. See Final
Act. 22.
3
Appeal2015-000023
Application 12/766,607
ANALYSIS
We have reviewed the Examiner's rejection in light of Appellants'
arguments that the Examiner erred. In reaching this decision, we consider
all evidence presented and all arguments made by Appellants.
Claims 1-3, 5, 6, and 26--28
Appellants argue W ojnarowski does not teach or suggest "removing a
portion of a back surface of the first semiconductor die," as recited in claim
1. App. Br. 55-57; Reply Br. 6-8. According to Appellants, it is not
possible to incorporate W ojnarowski' s method of removing material from
the die with Chow without the principle of operation of the prior art being
modified:
To remove a portion of the integrated circuit die would require
the integrated circuit die to be mounted with the back surface of
the die oriented away from the heat spreader in Chow. Mounting
the active surface of the integrated circuit die to the heat spreader
in Chow would negate the requisite interconnect between the
integrated circuit die and substrate.
App. Br. 56-57.
Appellants further argue W ojnarowski does "not show a method of
thinning a die before mounting the die." Reply Br. 7.
The Examiner finds W ojnarowski teaches removing a portion of a
back surface of a semiconductor die. Final Act. 19 (citing W ojnarowski
2:28-32). Additionally, the Examiner finds that modifying Chow so that the
material is removed prior to the semiconductor die being mounted would not
change the principal of operation of Chow. Ans. 4. The Examiner finds that
because claim 1 is not limited to removing the material after the
4
Appeal2015-000023
Application 12/766,607
semiconductor die has been mounted, removing material before mounting
the die teaches the disputed claim limitation. Id.
Appellants have not persuaded us that the Examiner erred. Claim 1 is
a method claim and "[i]t is improper to read a specific order of steps into
method claims unless "as a matter of logic or grammar, they must be
performed in the order written" or if the specification "directly or implicitly
requires such a narrow construction." Altiris Inc. v. Symantec Corp., 318
F.3d 1363, 1371 (Fed. Cir. 2003) (citation omitted). Appellants have not
pointed to any claim language or description in the Specification that would
require the removing step to be performed after the mounting step.
Accordingly, we agree with the Examiner and interpret the claim to allow
the removal of the material prior to mounting the semiconductor die.
Nor are we persuaded that the Examiner erred by Appellants'
argument that incorporating the W ojnarowski removal process into Chow
would result in a change in principle. In making the argument, Appellants
explain how it would not be possible to incorporate the W ojnarowski
removal process into Chow after the semiconductor die has been mounted.
See App. Br. 56-57; Reply Br. 7-8. However, "[t]he test for obviousness is
not whether the features of a secondary reference may be bodily
incorporated into the structure of the primary reference." In re Keller, 642
F.2d 413, 425 (CCPA 1981). Instead, the relevant issue is "what the
combined teachings of the references would have suggested to those of
ordinary skill in the art." Id. "Combining the teachings of references does
not involve an ability to combine their specific structures." In re Nievelt,
482 F.2d 965, 968 (CCPA 1973).
5
Appeal2015-000023
Application 12/766,607
In KSR International Co. v. Teleflex Inc., 550 U.S. 398, (2007), the
Supreme Court held that "if a technique has been used to improve one
device, and a person of ordinary skill in the art would recognize that it would
improve similar devices in the same way, using the technique is obvious
unless its actual application is beyond his or her skill." 550 U.S. at 417.
"The combination of familiar elements according to known methods is likely
to be obvious when it does no more than yield predictable results." Id. at
416; see also id. at 417 ("If a person of ordinary skill in the art can
implement a predictable variation, and would see the benefit of doing so,
§ 103 likely bars its patentability. ").
Although the specific examples in W ojnarowski involves the removal
of material after the semiconductor die is mounted, Appellants do not cite to
any portion of W ojnarowski that teaches away from removing material prior
to a final mounting.5 See Reply Br. 6-8. Nor do Appellants persuasively
argue that removing material from the semiconductor die "uniquely
challenging or difficult for one of ordinary skill in the art." Leapfrog
Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
(citing KSR, 550 U.S. at 418). Accordingly, Appellants' argument does not
demonstrate the Examiner's rejection is in error. Instead, we agree with the
5 We note that although the dice are placed in a die carrier in order to
remove materials from the die, following the removal of the materials, the
dice can be removed from the die carrier. See Wojnarowski 4:39--44 (The
die carrier being made "of any removable or dissolvable material that is
capable of being separated from dice 12 and 14, if so desired.");
Wojnarowski 6:42-55 (discussing removing the die from the die carrier after
thinning). Because a die can be removed from a die carrier after thinning,
one of ordinary skill in the art would have recognized that the thinned die
can be mounted as taught by Chow.
6
Appeal2015-000023
Application 12/766,607
Examiner that under KSR it would have been obvious to one of ordinary skill
in the art to the modify Chow to remove material from the semiconductor
die prior to the die being mounted.
Appellants also argue the Examiner erred in finding the prior art
teaches vertically aligned mounting as recited in claim 1. App. Br. 57-58;
Reply Br. 9-10. First, Appellants argue that a person of ordinary skill in the
art would not have modified Chow because it already solved the heat
dissipation problem. App. Br. 58. Second, Appellants argue that it would
not have been obvious to modify Chow in light of Liu-which would
involve changing the orientation of the active surface of the semiconductor
die-"because such a change would adversely affect the principles of
operation of Chow." App. Br. 58.
The Examiner finds Liu teaches mounting a first semiconductor die so
that the die, a portion of the electrical interconnect path and a portion of the
thermal conduction path are vertically aligned. Final Act. 20. The Examiner
further finds the one of ordinary skill in the art would have modified Chow
by arranging "a portion of the electrical interconnect path and a portion of
the thermal conduction path" to be vertically aligned with the semiconductor
die "as taught by Liu [in order] that the thermal conductive path can disport
more thermal flow from chip to the frame to reduce chip temperature."
Final Act. 20-21. The Examiner also finds that besides heat dissipation, the
vertical alignment taught by Liu also offers the advantage of reliability.
Ans. 5 (citing Liu i-f 18). The Examiner further concludes that the language
of claim 1 does not limit the orientation of the die active surface.
Appellants have not persuaded us that the Examiner erred. First, we
do not find Appellants' argument that Chow already solved the heat
7
Appeal2015-000023
Application 12/766,607
dissipation problems persuasive. Although Chow provides one solution to
the problem, we are not persuaded that a person of ordinary skill in the art
would not look for further improvements.
Second, Appellants' argument focuses on bodily incorporating the
orientation of the semiconductor from Liu into Chow. However, as
discussed supra, "[t]he test for obviousness is not whether the features of a
secondary reference may be bodily incorporated into the structure of the
primary reference." Keller, 642 F.2d at 425 (CCPA 1981). Instead, the
issue is whether Examiner erred in finding that a person of ordinary skill the
art would have modified Chow by locating "a portion of the electrical
interconnect path and a portion of the thermal conduction path" vertically
aligned with the semiconductor die. See Final Act. 20-21. Because
Appellants' argument does not address the reasoning relied on by the
Examiner and, thus, does not adequately address the rejection on appeal, we
are not persuaded the Examiner erred. Instead, we agree and adopt the
Examiner's findings. 6
According! y, we sustain the Examiner's rejection of claim 1, along
with the rejections of claims 2, 3, 5, 6, and 26-28, which are not argued
separately.
Claims 13 and 14
As noted in footnote 1, supra, claims 13 and 14 were identified by the
Examiner as both allowed and rejected. Appellants advance no arguments
6 Because we find the combination of Chow and Liu teach the vertically
aligned mounting limitation recited in claim 1, Appellants' argument that
Chow alone does not teach that limitation is moot.
8
Appeal2015-000023
Application 12/766,607
regarding the rejection of claims 13 and 14. Arguments not made are
considered waived. See 37 C.F.R. § 41.37(c)(l)(iv)(2012).
Accordingly, we proforma sustain the Examiner's rejection of claims
13 and 14.
Claims 15-25 and 33-36
Appellants argue Chow does not disclose "mounting a first
semiconductor die to the electrical interconnect path and thermal conduction
path of the interconnect structure," as recited in claim 15. App. Br. 59---61;
Reply Br. 11-13. Appellants note that the Examiner "identifies connection
pad 108, conductive adhesive 206, and system pad 214 as the interconnect
structure in claim 15." App. Br. 60. Appellants argue that Chow Figure 2
shows the semiconductor die "is mounted to heat spreader 102 using
conductive adhesive 206 and is electrically interconnected to substrate 106
using bond wires 208" and is not mounted to the electrical interconnect
path-items 108 and 214. App. Br. 60---6. According to Appellants, "a bond
wire 208 coupled to system pad 214 and connection pad 108 does not meet
the limitation of mounting a first semiconductor die to the electrical
interconnect path of the interconnect structure." Reply Br. 12; App. Br. 61.
The Examiner concludes that mounting is not limited to the specific
examples of mounting show in the Specification. Ans 7. Instead, the
Examiner finds that mounting is met by the features of adhesive to and
bonded to:
The reference to Chow has the mounting via the adhesive
bonding and the wire bonding. Chow's Figs.1-3 shows that the
chip 204 (the first semiconductor die) adhesive to heat spreader
102 (the thermally conductive frame) by the conductive adhesive
206 (the thermal conductive path) and bonded to wire 208 further
9
Appeal2015-000023
Application 12/766,607
Id.
connected to pad 214 and interconnect 108 (the electrical
interconnect path). Accordingly, the mounting feature is met by
the features of "adhesive to" and "bonded to."
We disagree with the Examiner as the Examiner has not identified
sufficient evidence or provided sufficient explanation as to how Chow
discloses "mounting a first semiconductor die to the electrical interconnect
path and thermal conduction path of the interconnect structure," as recited in
claim 15. "Mount" is defined as "to attach to a support." Merriam-
W ebster.com, http://www.merriam-webster.com/dictionary/mount (last
visited June 14, 2016). Although the Examiner finds a connection between
the semiconductor die and the electrical interconnect path, a connection is
not the same as mounting.
Accordingly, we are constrained on this record to reverse the
Examiner's rejection of claim 15, along with the rejection of claim 21,
which is argued on the same ground; and dependent claims 16-20; 22-25;
and 33-36.
DECISION
For the above reasons, we affirm the Examiner's rejection of claims
1-3, 5, 6, 13, 14, 26, 27, and 28.
For the above reasons, we reverse the Examiner's rejection of claims
15-25 and 33-36.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
10