Ex Parte Padmanabha et al

Patent Trial and Appeal Board

Nov 20, 2017

14093042 (P.T.A.B. Nov. 20, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/093,042 11/29/2013 Shruti Padmanabha JRL-550-1682 5822
23117 7590 11/22/2017
NIXON & VANDERHYE, PC
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
11/22/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon @ firsttofile. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHRUTI PADMANABHA, ANDREW LUKEFAHR,
REETUPARNA DAS, and SCOTT MAHLKE
Appeal 2017-007718
Application 14/093,0421
Technology Center 2100
Before TERRENCE W. McMILLIN, KARA L. SZPONDOWSKI, and
SCOTT B. HOWARD, Administrative Patent Judges.
McMILLIN, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the final
rejection of claims 1—8 and 10—20. Final Act. 1. Claim 9 stands objected to
for being dependent upon a rejected base claim but is, otherwise, allowable.
Final Act. 2. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 According to Appellants, the real party in interest is The Regents of the
University of Michigan. App. Br. 3.
Appeal 2017-007718
Application 14/093,042
REJECTIONS ON APPEAL
Claims 1, 15, 19, and 20 stand rejected under 35 U.S.C. § 102(a)(1) as
being anticipated by Schwinn et al. (US 2009/0293061 Al, published Nov.
26, 2009) (“Schwinn”). Final Act. 3.
Claim 16 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Schwinn and Official Notice. Final Act. 6.
Claims 2—8, 10-14, 17, and 18 stand rejected under 35 U.S.C. § 103
as being unpatentable over Schwinn, Cong et al. (Jason Cong & Bo Yuan,
Energy-Efficient Scheduling on Heterogeneous Multi-Core Architectures,
ACM/IEEE International Symposium on Low Power Electronics and Design
(2012) (“Cong”)), and Official Notice. Final Act. 6.
THE CLAIMED INVENTION
The present invention generally relates to “data processing systems,”
and more particularly to “the field of data processing systems having a
plurality of execution mechanisms for executing program instructions and
between which a selection may be made as to which execution mechanism is
active to execute the stream of program instructions at a given time.” Spec.
2. Independent claims 1 and 19 are directed to apparatus and independent
claim 20 is directed to a method. App. Br. 16, 21—23 (Claims App’x).
Claim 1 recites:
1. Apparatus for processing data under control of program
instructions, said apparatus comprising:
first execution circuitry configured to execute program
instructions;
second execution circuitry configured to execute said
program instructions, said second execution circuitry having a
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Application 14/093,042
lower energy consumption when executing said program
instruction than said first execution circuitry, and said second
execution circuitry requiring a longer time to execute said
program instructions than said first execution circuitry; and
control circuitry configured to control whether said
program instructions are executed by said first execution
circuitry or said second execution circuitry, wherein
said control circuitry comprises prediction circuitry
configured:
(i) to predict a predicted identity of a next
sequence of program instructions to be executed in
dependence upon a most recently executed sequence of
program instructions; and
(ii) in dependence upon said predicted identity, to
predict a predicted execution target corresponding to
whether said next sequence of program instructions
should be executed with said first execution circuitry or
said second execution circuitry; and
said control circuitry is configured to select either said
first execution circuitry or said second execution circuitry to
execute said next sequence of program instructions in
dependence upon said predicted execution target.
ANALYSIS
We have reviewed Appellants’ arguments in the Briefs, the
Examiner’s rejection, and the Examiner’s response to Appellants’
arguments. Appellants’ arguments have persuaded us of error in the
Examiner’s rejection of independent claim 1 under 35 U.S.C. § 102.
The dispositive issue presented by Appellants’ arguments is whether
the Examiner erred in finding that Schwinn describes “to predict a predicted
identity of a next sequence of program instructions to be executed in
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Application 14/093,042
dependence upon a most recently executed sequence of program
instructions,” as recited in claim 1, and similarly recited in independent
claims 19 and 20. App. Br. 8—14; Reply Br. 3—5.
In particular, Appellants contend Schwinn does not describe
“predicting ahead as to what will be the identity of the next sequence of
program instructions to be executed based on a most-recently executed
sequence of program instructions.” App. Br. 10—11. Appellants argue
neither Schwinn’s performance requirement nor Schwinn’s P tag bit
describes a “predicted identity of a next sequence of program instructions to
be executed” because they make “no prediction as to whether that associated
sequence of instructions is the next sequence of instructions to be executed.”
Reply Br. 3. Appellants further argue neither Schwinn’s performance
requirement nor Schwinn’s P tag bit is “determined in dependence on a most
recently executed sequence of instructions.” Reply Br. 3.
In response to Appellants’ arguments, the Examiner finds that
Schwinn’s “performance requirement for the task reads upon the claimed
identity” and is “based on runtime execution (i.e. most recently executed
sequence of instructions)” to control “how the task is executed by the
execution units in the processor both currently and in the future (i.e. next
sequence of program instructions).” Ans. 4.
We disagree with the Examiner’s findings. Schwinn describes
establishing a performance requirement during runtime of an application
executing on a processing unit, which maps instructions and their associated
tasks to a particular execution unit. Schwinn 173. In other words, Schwinn
may teach the establishment of a performance requirement that identifies a
mapping between instructions with a particular execution unit, and
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Application 14/093,042
separately Schwinn may teach establishing performance requirements during
runtime. However, these disclosures of Schwinn do not describe the claimed
“to predict a predicted identity of a next sequence ofprogram instructions to
be executed in dependence upon a most recently executed sequence of
program instructions” (emphasis added). See Schwinn, Fig. 8, 73, 75, 77,
79.
The Examiner has not made a findings that any other disclosure in
Schwinn describes the disputed limitation, nor has the Examiner made
findings that additional references provide teachings that make up for the
deficiency in the rejection of claim 1. Thus, we are constrained by the
record before us to reverse the Examiner’s rejection of independent claims 1,
19, and 20, and dependent claims 2—8 and 10-18.
DECISION
The rejections of claims 1—8 and 10—20 are reversed.
REVERSED
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