12145099 (P.T.A.B. Jan. 30, 2014)

Ex Parte Ortner

Patent Trial and Appeal BoardJan 30, 2014

12145099 (P.T.A.B. Jan. 30, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/145,099 06/24/2008 Joerg Ortner I560.215.101/2008P50609US 2736 25281 7590 01/30/2014 DICKE, BILLIG & CZAJA FIFTH STREET TOWERS 100 SOUTH FIFTH STREET, SUITE 2250 MINNEAPOLIS, MN 55402 EXAMINER LAURENZI, MARK A ART UNIT PAPER NUMBER 2894 MAIL DATE DELIVERY MODE 01/30/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte JOERG ORTNER __________ Appeal 2011-012836 Application 12/145,099 Technology Center 2800 ____________ Before ROMULO H. DELMENDO, BEVERLY A. FRANKLIN, and MICHAEL P. COLAIANNI, Administrative Patent Judges. COLAIANNI, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134 the final rejection of claims 1-10, 14, 16, and 26-28. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). Claims 11-13 were allowed by the Examiner (Ans. 11). We REVERSE. Appellant’s invention is directed to a semiconductor chip having a first mark (306) for identifying a position of the chip within an exposure field and a first matrix (308) in a first layer of the chip and a second mark Appeal 2011-012836 Application 12/145,099 2 within the first matrix identifying a position of the exposure field on a wafer (300) (Spec. 1: 19-23; Fig. 5). Claim 1 is illustrative: 1. A semiconductor chip comprising: a first mark for identifying a position of the chip within an exposure field; a first matrix in a first layer of the chip; and a second mark within the first matrix identifying a position of the exposure field on a wafer. Appellant appeals the following rejections: 1. Claims 1-3 and 26-28 are rejected under 35 U.S.C. § 103(a) as unpatentable over Hashimoto (JP 410041210 A, published Feb. 13, 1998) in view of Werner et al. (US 6,724,096 B2, issued Apr. 20, 2004) and Lee (US 5,350,715, issued Sept. 27, 1994). 2. Claims 4, 5, and 7-10 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Hashimoto in view of Werner, Lee, and Kotani et al. (US 2009/0277004 A1, published Nov. 12, 2009). 3. Claim 6 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Hashimoto in view of Werner, Lee, Kotani, and Tippetts (US 4,192,449, issued Mar. 11, 1980). 4. Claim 14 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Werner in view of Kotani and Lee. 5. Claim 16 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Werner in view of Kotani, Lee, and Hashimoto. Appeal 2011-012836 Application 12/145,099 3 ISSUE Did the Examiner reversibly err in determining that it would have been obvious “to replace the an [sic] identification measure as taught by Hashimoto in view of Werner [or Werner in view of Kotani] with the measure of chip identification as taught by Lee” (Ans. 5, 10) and so render obvious the subject matter of independent claims 1, 14, and 26? We decide this issue in the affirmative. FINDINGS OF FACT & ANALYSIS Appellant argues that using Lee’s pattern of dots in place of the alignment marks taught by Hashimoto and Werner would have rendered Hashimoto and Werner unsuitable for their intended purpose of aligning exposure fields on a wafer during lithography processes (App. Br. 10, 25). Appellant contends that Hashimoto and Werner use identical alignment marks in each exposure field that can be measured by a lithography system, while Lee discloses a unique pattern of dots on each semiconductor chip that could not be used by Hashimoto’s or Werner’s lithography systems for alignment of during lithography processes. Id. The Examiner’s finding and conclusions regarding Hashimoto, Werner, Kotani, and Lee are located on pages 4-6, and 9-10 of the Answer. The Examiner finds that Hashimoto or Werner teaches forming alignment marks on the surface of a chip which corresponds to the claimed “first mark for identifying a position of the chip within an exposure field” (Ans. 4, 9). The Examiner finds that Hashimoto and Werner fail to disclose a matrix with an identifying mark that indicates the location of the exposure field on the wafer (Ans. 4-5). The Examiner finds that Werner discloses using an Appeal 2011-012836 Application 12/145,099 4 alignment structure to locate the corner of an exposure field (Ans. 5). The Examiner finds that Lee discloses using an m x n matrix of binary indicia as an identification mark. The Examiner concludes that it would have been obvious [T]o replace the an [sic] identification measure as taught by Hashimoto in view of Werner [or Werner in view of Kotani] with the measure of chip identification as taught by Lee, since the selection of the specific shapes and geometries of an identification mark is dependent upon various design parameters that are well recognized to be equivalent measures of providing identification (Ans. 5-6, 10). The Examiner never responds to Appellant’s argument that replacing Hashimoto’s or Werner’s alignment structures with Lee’s pattern of dots would have rendered Hashimoto or Werner unsuitable for its intended purpose. Nevertheless, Hashimoto and Werner each discloses forming alignment marks on a chip formed on a wafer. Werner discloses that the alignment marks are used to properly align the wafers in an automated measurement process (col. 1, ll. 66-67; col. 2, ll. 1-2; 35-45). Werner discloses that the alignment markings are a series of elongated patterns called delineation regions (i.e., 110, 111, 112, and 113) that are formed in the material layer of the chip (col. 2, ll. 25-30; Fig. 1 and 3). Hashimoto discloses that the alignment marks aid in improving the accuracy of superposing the position of two or more chips (para. [0017]). Hashimoto discloses using the alignment marks to position the chip and the reduced projection device (i.e., stepper) (paras. [0002], [0028]). In contrast, Lee discloses forming distinct markings on individual semiconductor chips fabricated on a common semiconductor wafer with the Appeal 2011-012836 Application 12/145,099 5 identification mark representative of the location of the respective chip on the wafer (col. 2, ll. 24-29). Lee discloses that the chip identification consists of a matrix of dots, wherein the dot pattern signifies the original location of the chip to which it is affixed on the wafer on which it was fabricated (col. 1, ll. 60-65). Lee does not disclose that the markings may be used as alignment markings. The Examiner has not explained why one of ordinary skill in the art would have replaced Hashimoto’s or Werner’s alignment markings with Lee’s identification markings. Rather, the Examiner improperly characterizes Hashimoto’s and Werner’s markings as identification markings despite the Examiner finding that Hashimoto and Werner disclose alignment markings (Ans. 4-5). There appears to be a distinction between alignment markings and identification markings which the Examiner fails to address adequately. The Examiner provides no specific findings or analysis regarding whether the dot matrix identification markings of Lee would have been capable of functioning as alignment markings on the semiconductor wafer or chip despite Appellant’s argument thereto (App. Br. 10). On this record, the preponderance of the evidence favors Appellant’s argument of nonobviousness. DECISION The Examiner’s decision is reversed. ORDER REVERSED cdc