Ex Parte Onde et al

Patent Trial and Appeal Board

Sep 29, 2016

13536712 (P.T.A.B. Sep. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/536,712 06/28/2012
38106 7590 10/03/2016
Seed IP Law Group LLP/ST (EP ORIGINATING)
701 FIFTH AVENUE, SUITE 5400
SEATTLE, WA 98104-7092
Vincent Onde
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
852663.613 6681
EXAMINER
VALLECILLO, KYLE
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
10/03/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
Patentlnfo@SeedIP.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VINCENT ONDE and DRAGOS DA VIDESCU
Appeal2015-006824
Application 13/536,712
Technology Center 2100
Before JEAN R. HOMERE, JOHN A. EV ANS, and
DANIEL J. GALLIGAN, Administrative Patent Judges.
Per Curiam.
DECISION ON APPEAL 1
Appellants2 seek our review under 35 U.S.C. § 134(a) of the
Examiner's final rejection of claims 1-21. App. Br. 2. We have jurisdiction
under 35 U.S.C. § 6(b).
We affirm.
1 Our Decision refers to Appellants' Appeal Brief filed December 23, 2014
("App. Br."); Appellants' Reply Brief filed July 13, 2015 ("Reply Br.");
Examiner's Answer mailed May 13, 2015 ("Ans."); the Final Office Action
mailed June 24, 2014 ("Final Act."); and original Specification filed June
28, 2012 ("Spec.").
2 Appellants identify ST MICROELECTRONICS (ROUSSET) SAS as the
real party in interest. App. Br. 2.
Appeal2015-006824
Application 13/536,712
STATEMENT OF THE CASE
Claims on Appeal
Claims 1, 8, and 15 are independent claims. Claim 1 is reproduced
below (with disputed limitations in italics):
1. A method to process faults in a control unit, the method
compnsmg:
upon each request to read a datum in a first memory, received
by a first interface circuit configured to access the first memory,
calculating by the first interface circuit a check word based on the
datum read;
if the calculated check word is different from a check word read
by the first interface circuit in the first memory in association with the
datum read, activating by the first interface circuit an error signal;
and
sending the error signal to an output circuit of the control unit
without using other circuits of the control unit configured to send a
request to access the first memory.
References
Marshall et al. us 5,915,082 June 22, 1999
Laberge et al. us 6,012,148 Jan. 4, 2000
Seo et al. US 2006/0069948 Al Mar. 30, 2006
Grimonpont et al. US 2011/0022903 Al Jan. 27, 2011
Examiner's Rejections
Claims 1, 2, 7-9, 15, and 16 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Grimonpont et al. Final Act. 2-5.
Claims 3, 10-12, and 17-19 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Grimonpont and Seo. Final Act. 6-8.
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Application 13/536,712
Claims 4---6 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Grimonpont, Marshall, and Laberge. Final Act. 8-11.
Claim 13 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Grimonpont, Seo and Laberge. Final Act. 11-12.
Claim 14 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Grimonpont, Seo, Laberge, and Marshall. Final Act. 12-13.
Claim 20 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Grimonpont and Laberge. Final Act. 13-14.
Claim 21 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Grimonpont, Laberge, and Marshall. Final Act. 14--15.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner erred. See App. Br. 13-25; Reply Br. 2---6. We
are not persuaded by Appellants' arguments. We highlight and address
specific arguments and findings for emphasis as follows.
Appellants contend the Examiner erred in finding Grimonpont teaches
acts recited in independent claim 1 to be performed by the recited "first
interface circuit." App. Br. 13-21; Reply Br. 2---6. In particular, Appellants
argue Grimonpont does not teach any structure corresponding to the recited
"first interface circuit" that
performs the acts of receiving a request to read a datum in a first
memory, calculating a check word based on a datum read from the
first memory, reading a check word in the first memory, and [if] the
calculated check word is different from the check word read from the
first memory, ... activating an error signal.
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Application 13/536,712
App. Br. 13 (emphasis omitted). Appellants assert that the Examiner's
reliance upon the combination of the Field Programmable Gate Array
(FPGA) component 105 and the error detection and correction means 130 to
teach the recited "first interface circuit" is improper. App. Br. 19 (citing
Grimonpont Fig. 1 ). Appellants note Grimonpont teaches that the error
detection and correction means 130 may detect an error occurring in FPGA
component 105 which may be caused by a radiative environment. App. Br.
15 (citing Grimonpont i-f 70, Fig. 1 ). Appellants further note some of the
errors that require correction occur inside the FPGA component 105. App.
Br. 19. Appellants contend the combined circuit relied upon to the teach the
first interface circuit would be required to have the same type of memory
throughout, either random access memory (RAM) or other than RAM
memory. Id. Appellants argue the combined circuit would fail its intended
purpose of monitoring a RAM-based type FPGA component 105 with a
separate non-RAM-based error detection and correction means 130. App.
Br. 19, 22; Reply Br. 3. Appellants additionally argue the combination is
improper because the FPGA component 105 does not have access to the
reference spaces in memory 140 even though the error detection and
correction means 130 does. App. Br. 20 (citing Grimonpont i-f 74, Fig. 1).
The Examiner finds the FPGA component 105 in combination with
error detection and correction means 130 teaches the recited "first interface
circuit," including performing the recited functions. Ans. 5 (citing
Grimonpont Fig. 1 ). The Examiner interprets "first interface circuit," and
we agree, as a system of electrical components forming a common boundary
among components. Ans. 7. The Examiner finds the combination of the
FPGA component 105 and the error detection and correction means 130
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Application 13/536,712
reads the datum in the working space of memory 140 and determines the
presence of an error by comparing the datum read in the working space with
its corresponding reference datum from the reference space of memory 140.
Ans. 9 (citing Grimonpont i-fi-175-76, Fig. 1). We are not persuaded by
Appellants' assertion that one of ordinary skill in the art would be led away
from this arrangement taught in Grimonpont. Reply Br. 5. The Examiner
relies on a single embodiment taught in Grimonpont. Ans. 9 (citing
Grimonpont i-fi-1 7 5-7 6, Fig. 1 ). Ans. 9 (citing Grimonpont i-fi-1 7 5-7 6, Fig. 1 ).
The comparison may involve either a direct comparison of the data or
verification by control codes such as a cyclic redundancy codes (CRC)
calculated from the datum compared with a reference result stored in the
reference space. See Grimonpont i-fi-1 71-72, cited in Final Act. 3; see Ans.
10. This is consistent with Appellants' description of the first interface
circuit. Reply Br. 4 (citing Spec. 6). The Examiner finds the combination of
a RAM-based FPGA component 105 and a non-RAM error detection and
correction means 130 carries out the recited functions. Ans. 12 (citing
Grimonpont i-fi-175-76, Fig. 1). In particular, the Examiner finds
Grimonpont teaches restricting access of FPGA component 105 from the
reference spaces of memory 140 in the presence of detected errors to prevent
pollution of the reference spaces, yet permitting access to reference spaces
of the error detection and correction means 130. Ans. 12-13 (citing
Grimonpont i-fi-154, 74, Fig. 1). Grimonpont teaches that the error detection
and correction means 130 can continue to check for errors while the polluted
working space is disabled temporarily. See Grimonpont i175. The
Examiner explains the restriction of access to reference spaces of memory
140 to a portion of the combination does not change the respective functions
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Application 13/536,712
of the combination. Ans. 13. Thus, we are not persuaded the Examiner
erred in finding that FPGA component 105 and error detection and
correction means 130 in Grimonpont teach the recited "first interface
circuit."
Appellants argue the recited "first interface circuit" provides an
advantage over the components of Grimonpont. App. Br. 21-23.
Appellants assert providing a first interface circuit with the ability to test
memory, separate from a control unit, overcomes the slowness and the
inability to test memory where the main task is operating in the prior art.
App. Br. 21-22 (citing Spec. 1-2). Appellants contend the components in
Grimonpont as a combined device either would not be able to detect all of
the errors including errors in the components themselves or would violate
the restriction on memory 140 access. App. Br. 21 (citing Grimonpont i-fi-1
54, 74), 22, 23; Reply Br. 5. Appellants also argue the combined device
would slow down operations of the FPGA component 105 with only one bus
coupling the combined device to memory 140. App. Br. 23. Appellants
contend the Examiner provides no motivation why one of skill in the art
would interpret the components in Grimonpont combined as a single circuit.
Reply Br. 5.
The Examiner finds Appellants' citation to Appellants' Specification
does not describe how a single interface circuit provides an advantage to
components taught in Grimonpont. Ans. 14 (citing Spec. 1-2). We agree
with the Examiner that neither the performance nor the function of FPGA
component 105 and of error detection and correction means 130 would be
affected by an inference that these components act as a single component.
Ans. 14. In rejecting the rigid "teaching, suggestion, or motivation"
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Application 13/536,712
approach to the obviousness analysis, the Supreme Court stated, "[t]he
combination of familiar elements according to known methods is likely to be
obvious when it does no more than yield predictable results." KSR Int 'l Co.
v. Teleflex Inc., 550 U.S. 398, 415-16 (2007). Here, the Examiner has not
relied upon a modified arrangement of the components in Grimonpont
different from the arrangement taught in Grimonpont. Ans. 14. Rather, the
Examiner finds the components in Grimonpont perform equally as well as
separate components or as a single circuit. Final Act. 4. As such, we are not
persuaded the Examiner erred in concluding the subject matter of claim 1
would have been obvious over Grimonpont.
Appellants do not present additional persuasive arguments regarding
claims 2-7 which depend from claim 1. App. Br. 13; Reply Br. 6. With
respect to claims 8-21, Appellants do not present additional persuasive
arguments. App. Br. 23-25; Reply Br. 6.
DECISION
We affirm the Examiner's rejection of claims 1-21.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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