Ex Parte Offen et al

Patent Trial and Appeal Board

Feb 10, 2015

12057601 (P.T.A.B. Feb. 10, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte ZEEV OFFEN, ARIEL BERKOVITS, THOMAS A.
PIAZZA, ROBERT L. FARRELL, ALTUG KOKER, and
OPHER KAHN
____________________

Appeal 2012-009358
Application 12/057,601
Technology Center 2600
____________________

Before JEAN R. HOMERE, MICHAEL J. STRAUSS, and
NORMAN H. BEAMER, Administrative Patent Judges.

STRAUSS, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1–25. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
The claims are directed to a technique to share information among
different cache coherency domains. Abstr. Claim 1, reproduced below, is
illustrative of the claimed subject matter:
1. An apparatus comprising:
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a first cache and a second cache within a graphics logic
coherency domain, wherein the first cache is at a lower level in
a cache hierarchy than the second cache;
a central processing unit (CPU) to access information
stored in the first cache using a physical address, wherein the
CPU is in a different coherency domain than the graphics logic.

REFERENCE
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Andrews US 2006/0098022 A1 May 11, 2006

REJECTIONS
The Examiner made the following rejections:
Claims 1–11 and l3–25 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Andrews. Ans. 5–9.
Claim 12 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Andrews. Ans. 9.

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred in rejecting independent claims 1, 7,
13, and 19 under 35 U.S.C. § 102(b) as being anticipated by Andrews. We
agree with Appellants’ arguments as to this rejection of the claims.
Appellants contend Andrews’s tail pointer 1114 “would not be viewed
as a cache at all, by a person of ordinary skill in the field of the invention.”
App. Br. 11. Appellants argue “Andrews does not disclose that the GPU
[(graphics processing unit)] module 1112 has a first and a second cache.”
Id. at 13. According to Appellants:
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Andrews also describes, for example that, “the GPU module
may write a tail pointer to some type of coherent cacheable
memory (e.g., that is cacheable but is not itself cache)” (see
p.12, §B.3.l, par. 112, Fig. 17). So Andrews is careful to be
clear about what is, and what is not cache, and points out that
just because something is cacheable, that does not make it a
cache.
Id.
The Examiner responds by quoting from paragraph 112 of Andrews
describing that the GPU may write the tail pointer into a cacheable memory
and quoting from paragraph 114 describing “‘[f]or some embodiments, as
illustrated in FIG. 18, the tail pointer may be written to cache coherent
memory (CCM) 1700 located at, or otherwise accessible to, bus interface
logic 1800 used to communicate with GPU module 1112.’” Ans. 10.
We agree with Appellants the Examiner has erred. We do not agree
with the Examiner that either tail pointer 1114 is a cache or, if stored in GPU
modules 1112, is stored in a cache. To the contrary, we agree with
Appellants that Andrews makes clear neither tail pointer 1114 nor coherent
cacheable memory is a cache: “[f]or some specific embodiments, the GPU
module may write a tail pointer to some type of coherent cacheable memory
(e.g., that is cacheable but is not itself cache), as shown in FIG. 17.”
(Andrews ¶ 112). Nor has the Examiner explained why cache coherent
memory 1700 discloses cache, particularly in view of Andrews’s description
of “coherent cacheable memory . . . is not itself cache.” We further note
Andrews clearly identifies and labels cache by and with the associated cache
level, e.g., L1 (level 1) and L2 (level 2) caches 1008 and 1010. Id. ¶ 114.
There is no corresponding level designation of CCM 1700 as depicted in
Figure 18.
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Therefore, absent sufficient evidence or explanation, the Examiner
leaves us to speculate whether a cache coherent memory is a memory that,
for example, interfaces with a cache or is itself a cache. Although we do not
necessarily agree with Appellants that “Andrews discloses that cache
coherent memory is not cache” (Reply. Br. 3, emphasis added), neither has
the Examiner persuaded us that it is a cache. Therefore, because Andrews
discloses storing tail pointer 1114 in either (i) a coherent cacheable memory
which is NOT a cache or (ii) a cache coherent memory which is not
specifically identified as a cache, we agree with Appellants that Andrews
fails to disclose the disputed second cache within a graphics logic coherency
domain as required by claim 1. Therefore we do not sustain the rejection of
claim 1 under 35 U.S.C. § 102(b) as being anticipated by Andrews nor the
rejection of dependent claims 1–6. Although Appellants raise additional
contentions of error in connection with claim 1, we do not reach them as our
resolution of this contention is dispositive of the appealed rejections under
35 U.S.C. § 102(b).
In connection with claim 7, the Examiner finds numerals 1118, 1108,
and 1110 depicted in Figure 11 of Andrews disclose CPU level-1 (L2) cache,
a CPU mid-level cache (MLC), and a last level cached (LLC) as required by
the claim. Ans. 6. However, in the absence of any description in Andrews
or explanation by the Examiner, we agree with Appellants that path 1118 is
not described as, and fails to disclose, a cache. Nor does, for the reasons
supra, tail pointer 1114 disclose a cache. App. Br. 16–17, Reply Br. 5.
Therefore we do not sustain the rejection of claim 7 under 35 U.S.C.
§ 102(b) as being anticipated by Andrews or the rejection of dependent
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claims 8–11. For similar reasons, we do not sustain the rejection of
dependent claim 12 under 35 U.S.C. § 103(a) over Andrews.
In connection with claim 13 the Examiner again relies on Figures 11–
12 of Andrews for disclosing caches, claim 13 instead requiring L1 and
MLC. Ans. 7. Appellants contend Andrews fails to disclose the recited
caches substantially for the reasons discussed supra. See App. Br. 19–20. In
the absence of a clear mapping of the caches of claim 13 to the elements
depicted in Figures 11 and 12 of Andrews or other explanation in support of
the rejection, and for the reasons supra, we agree with Appellants that
Andrews fails to disclose the L1 cache and MLC of claim 13. Therefore, we
do not sustain the rejection of claim 13 under 35 U.S.C. § 102(b) as being
anticipated by Andrews or the rejection of dependent claims 14–18.
In connection with claim 19, Appellants contend “the CPU and the
GPU module described by Andrews are of the same (not different)
coherency domain(s).” App. Br. 21. Appellants refer back to the argument
presented in connection with claim 1 (id.), therein arguing “since only one
shared cache, L2 1110, [of Andrews] is associated with the GPU module
1112, and since CPU n 1102 and L2 1110 are clearly . . . in the same
coherency domain, CPU n 1102 and GPU module 1112 must be in the same
coherency domain. Accordingly, CPU n 1102 is not in a different coherency
domain than the GPU module 1112” (id. at 15).
The Examiner responds:
Because the claim language does not specify the scope of the
“CPU coherency domain”, the examiner interprets it as the
difference in functionality between the CPU and the GPU (par.
[0055], ...In one exemplary implementation, the CPUs (108,
110, . .. 112) differ (from the functionality provided by the GPU
module 104 in a number of respects; for instance, the CPUs
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(108,110, . .. 112) typically have a much more general software
programming model, perform[s] significantly better on single
threaded applications, and enable more decision-based
branching than the GPU module 104, emphasis added).
Ans. 10. Appellants reply, arguing the Examiner’s interpretation is improper
because, based on both the Specification and Andrews’s disclosure, one
skilled in the art “would interpret a CPU in a different cache coherency
domain than the graphics logic to mean that there were some differences
between how the respective cache resident data remains coherent with main
memory.” Reply Br. 7.
We agree the Examiner’s interpretation is improper. We note the
Examiner erroneously refers to the term CPU coherency domain instead of
the recited CPU cache coherency domain and GPU cache coherency
domain. Ans. 10. That is, the respective domains involve cache features,
not merely CPU and GPU functionality in general as per the Examiner’s
interpretation. See id. Instead, we find reasonable Appellants’ interpretation
that cache domains are based on how the respective cache resident data
remains coherent with main memory. See Reply Br. 7. Based on this
interpretation, we further agree with Appellants that “a GPU cache
coherency domain, different from the CPU cache coherency domain, as set
forth in Claim 19, is not found, either expressly or inherently described by
the disclosure of Andrews.” App. Br. 21. Therefore we do not sustain the
rejection of claim 19 rejected under 35 U.S.C. § 102(b) as being anticipated
by Andrews or the rejection of dependent claims 20–25.

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DECISION
The Examiner’s decision to reject claims 1–25 is reversed.

REVERSED

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