Ex Parte O et al

Patent Trial and Appeal Board

Aug 6, 2018

14704044 (P.T.A.B. Aug. 6, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/704,044 05/05/2015
16501 7590
Timothy M. Honeycutt
Attorney at Law
37713 Parkway Oaks Ln.
Magnolia, TX 77355
08/08/2018
FIRST NAMED INVENTOR
Sean M. O'Mullan
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AMDI:308\HON 4317
EXAMINER
HAGAN, SEAN P
ART UNIT PAPER NUMBER
2828
NOTIFICATION DATE DELIVERY MODE
08/08/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
timhoney@sprynet.com
timhoneycutt@earthlink.net
elizabethahoneycutt@earthlink.net
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SEAN M. O'MULLAN,
MICHAELS. ALFANO,
and BRYAN BLACK
Appeal2017-010286
Application 14/704,044 1
Technology Center 2800
Before ADRIENE LEPIANE HANLON, MICHAEL P. COLAIANNI, and
N. WHITNEY WILSON, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellants filed an appeal under 35 U.S.C. § 134(a) from an Examiner's
decision finally rejecting claims 1-21. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM.
1 The real party in interest is said to be Advanced Micro Devices, Inc. Appeal
Brief dated February 17, 2017 ("App. Br."), at 4.
Appeal2017-010286
Application 14/704,044
The claims on appeal are directed to an apparatus and a method of
manufacturing wherein a second semiconductor chip includes offloaded logic of a
first semiconductor chip. Representative claim 1 is reproduced below from the
Claims Appendix of the Appeal Brief.
1. An apparatus, comprising:
an interposer;
a first semiconductor chip mounted on the interposer; and
a second semiconductor chip mounted on, and electrically
connected to the first semiconductor chip by, the interposer, the
second semiconductor chip including offloaded logic of the first
semiconductor chip.
App. Br. 25 ( emphasis added).
The following grounds of rejection are maintained on appeal:
(1) claims 1--4, 8-12, and 15-19 under 35 U.S.C. § I02(a)(l) as
anticipated by Goel;2
(2) claims 5, 13, and 20 under 35 U.S.C. § 103 as unpatentable over Goel
in view of Eldridge et al.; 3 and
(3) claims 6, 7, 14, and 21 under 35 U.S.C. § 103 as unpatentable over
Goel.
B. DISCUSSION
1. Claims 1-5, 8-13, and 15-20
The Examiner finds Goel discloses an interposer, a first semiconductor chip
(2300 in Figure 2) mounted on the interposer, and a second semiconductor chip
2 US 2013/0047046 Al, published February 21, 2013 ("Goel").
3 US 2004/0004216 Al, published January 8, 2004 ("Eldridge").
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(2200 in Figure 2; 3100 in Figure 34) mounted on, and electrically connected to the
first semiconductor chip by, the interposer. The Examiner finds the second
semiconductor chip includes offloaded logic of the first semiconductor chip. Final
5.5
The Appellants argue that Goel's second semiconductor chip (i.e., logic die
3200) does not include offloaded logic of the first semiconductor chip. App. Br.
1 7. The Appellants argue that:
"[O]ffloaded logic" is logic in a first semiconductor chip that would,
in a conventional design, be implemented in a second semiconductor
chip. This logic would be offloaded from the second semiconductor
chip and implemented in the first semiconductor chip with an
interposer serving as a high speed, high bandwidth bus between the
two. The offloaded logic can take a variety of forms. A non-
exhaustive list includes data path logic, design-for-test (DPT) circuits
or other logic.
App. Br. 17 ( emphasis added).
The Appellants argue that "there is no indication that the logic die 3200
[ corresponding to the claimed second semiconductor chip] includes logic that
would, in a conventional design, be implemented in the DRAM die 3300
[corresponding to the claimed first semiconductor chip]." App. Br. 20-21.
The Examiner finds that "reference to a 'conventional design' in the
proposed definition requires some clear definition of what a 'conventional design'
is so as to provide a specific point of comparison yet no explanation constraining a
'conventional design' is provided." Ans. 3. 6 Therefore, the Examiner interprets
4 There appears to be no dispute on this record that logic die 3200, corresponding
to the claimed second semiconductor chip, is mislabeled 3100 in Goel Figure 3.
Final 5; App. Br. 17.
5 Final Office Action dated September 16, 2016.
6 Examiner's Answer dated June 5, 2017.
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Application 14/704,044
"offloaded logic" to mean "logic that is in some way related to the first chip but is
present on the second chip and not the first chip." Ans. 3.
Consistent with the Examiner's interpretation of "offloaded logic," the
Examiner finds that second semiconductor chip or logic die 3200 includes
offloaded logic. Ans. 4. More specifically, the Examiner finds that:
[L ]ogic die 3200 includes logic which is not present on DRAM die
3300 as indicated by p. [0025] detailing the presence of logic on die
3200. Further, the logic present on chip 3200 is related to chip 3300
by forming the interface between chip 3300 and the external system as
described in p. [0025]. As such, it is determined that logic on chip
3200 is offloaded from chip 3300 by not being present on chip 3300
and yet operating on chip 3300 in accordance with the interpretation
of the term "offloaded logic" set forth [above].
Ans. 4 (emphasis added).
The Examiner's interpretation of "offloaded logic" is supported by the
record. According to the Appellants' Specification,
[I]n [an] illustrative embodiment the semiconductor chip 20 may be a
processor and the semiconductor chip 25 may be an integrated circuit
that includes logic that would, in a conventional design, be
implemented in the semiconductor chip 20. This logic is offloaded
from the semiconductor chip 20 and implemented in the
semiconductor chip 25 .... The offloaded logic can take a variety of
forms. A non-exhaustive list includes data path logic, design-for-test
(DPT) circuits or other logic .... At the design stage for the
semiconductor chip 20 and the semiconductor chip 25 ... , logic of
the semiconductor chip 20 ... is selected to be offloaded to the
semiconductor chip 25. That logic is then eliminated from the design
and manufacture of the semiconductor chip 20 but incorporated into
the design and manufacture of the semiconductor chip 25.
Spec. ,r 23 ( emphasis added).
Based on the Appellants' Specification, we interpret the phrase "offloaded
logic" to be selected logic that is eliminated from the design and manufacture of a
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Application 14/704,044
first semiconductor chip and incorporated into a second semiconductor chip. See
Spec. ,r 23. We interpret the word "offloaded" to describe the process of relocating
selected logic from one semiconductor chip to another semiconductor chip.
Therefore, we conclude that claim 1, which recites "the second semiconductor chip
including offloaded logic of the first semiconductor chip,"7 is in product-by-
process format.
It is well settled that the patentability of a claim in product-by-process
format is determined based on the product itself, not on the method of making it.
See In re Thorpe, 777 F.2d 695, 697 (Fed. Cir. 1985) ("If the product in a product-
by-process claim is the same as or obvious from a product of the prior art, the
claim is unpatentable even though the prior product was made by a different
process.").
In this case, the Examiner finds that logic die 3200 (corresponding to the
claimed second semiconductor chip) includes logic that is not present on DRAM
die 3300 ( corresponding to the claimed first semiconductor chip), and thus satisfies
the limitation "the second semiconductor chip including offloaded logic of the first
semiconductor chip" 8 recited in claim 1. Ans. 4 ( citing Goel ,r 25).
The Examiner's finding is supported by the record. According to the
offloading process described in the Appellants' Specification, selected logic is
eliminated from a first semiconductor chip and is incorporated into a second
semiconductor chip. Spec. ,r 23. Thus, as in Goel, selected logic present on the
claimed second semiconductor chip is not present on the claimed first
semiconductor chip after the offloading process is performed.
7 App. Br. 25 ( emphasis added).
8 App. Br. 25 ( emphasis added).
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Where, as here, the prior art product appears to be identical to the claimed
product, the burden is on the Appellants to present evidence establishing an
unobvious difference between the claimed product and the prior art product. In re
Marosi, 710 F.2d 799, 803 (Fed. Cir. 1983). The Appellants have not satisfied that
burden. Therefore, the anticipation rejection of claim 1 is sustained.
The Appellants do not present arguments in support of the separate
patentability of any of claims 2-5, 8-13, and 15-20. 9 App. Br. 21-22. Therefore,
the anticipation rejection of claims 2--4, 8-12, and 15-19 and the obviousness
rejection of claims 5, 13, and 20 also are sustained.
2. Claims 6, 7, 14, and 21
Claim 7 depends from claim 1 and recites "wherein the first semiconductor
chip comprises circuits of a first process node and the offloaded logic comprises
circuits of a second process node of larger geometry than the first process node."
App. Br. 26 ( emphasis added).
The Examiner finds Goel does not disclose the limitation recited in claim 7.
Final 9. Nonetheless, the Examiner "takes Official Notice of the fact that it was
known in the art that semiconductor dies may be made with different architectures
9 Independent method claim 8 recites the step of "providing a second
semiconductor chip, the second semiconductor chip including offloaded logic of
the first semiconductor chip." App. Br. 26 ( emphasis added). Similarly,
independent method claim 15 recites the step of "fabricating a second
semiconductor chip, the second semiconductor chip including offloaded logic of
the first semiconductor chip." App. Br. 28 ( emphasis added). Significantly, claims
8 and 15 do not recite the active step of offloading selected logic from a first
semiconductor chip onto a second semiconductor chip. Thus, for the reasons set
forth above, the phrase "offloaded logic" in claims 8 and 15 does not patentably
distinguish the claimed second semiconductor chip from logic die 3200 described
in Goel ( corresponding to the claimed second semiconductor chip).
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and that such different architectures exhibit differences in cost, footprint, and
speed." Final 9-10. The Examiner concludes that it would have been obvious to
one of ordinary skill in the art to select different process node geometries for the
noted dies in Goel "since it has been held that discovering an optimum value of a
result effective variable involves only routine skill in the art." Final 10 ( citing In
re Boesch, 617 F.2d272 (CCPA 1980)).
The Appellants do not challenge the Examiner's finding of Official Notice
or direct us to any error in the Examiner's conclusion of obviousness. Rather, the
Appellants contend that "Goel makes no mention of nor hints at any mismatched
process geometry nodes between two semiconductor chips mounted on an
interposer where the mismatched geometry pertains to the offloaded logic." App.
Br. 23. As correctly pointed out by the Examiner, Goel is not cited as teaching the
limitation recited in claim 7. Ans. 4.
For the reasons set forth above, the obviousness rejection of claim 7 is
sustained. The Appellants do not present arguments in support of the separate
patentability of any of claims 6, 14, and 21. See App. Br. 22-23. Therefore, the
obviousness rejection of claims 6, 14, and 21 also is sustained.
C. DECISION
The Examiner's decision is affirmed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(l ).
AFFIRMED
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