Ex parte NobleDownload PDFBoard of Patent Appeals and InterferencesJan 30, 200108365617 (B.P.A.I. Jan. 30, 2001) Copy Citation The opinion in support of the decision being entered today was not written for publication in a law journal and is not binding precedent of the Board. Paper No. 39 UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte WENDELL P. NOBLE, JR. ____________ Appeal No. 1998-3078 Application No. 08/365,617 ____________ ON BRIEF ____________ Before HAIRSTON, BARRY, and LEVY, Administrative Patent Judges. BARRY, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134 from the rejection of claims 1-15, 24, and 26-28. We reverse. BACKGROUND The invention at issue in this appeal relates to dynamic random access memory (DRAM) cell. A DRAM cell consists of a transistor and a capacitor, both formed on a semiconductor substrate, and interconnects formed by a layer of a conductor on top of the substrate and in contact with the gate of the Appeal No. 1998-3078 Page 2 Application No. 08/365,617 transistor. Besides the transistor and capacitor, the substrate level includes a "strap" connecting a given transistor to a given capacitor and the required isolation between cells. The interconnect level includes wordlines that interconnect the gate electrodes of transistors in DRAM cells and sufficient space between the wordlines to prevent shorting therebetween. As such, the total area taken up by a given DRAM cell is determined by the larger of the area of all the structures on the silicon substrate level and the area of the connectors and spaces therebetween on the connector level. Whichever of these two is larger determines the area of the cell. The appellant's invention uses segment gates and spacer wordlines to save area on the connector level of a DRAM cell. Because the total area of each cell could not be correspondingly reduced unless the area of each cell at the silicon substrate level was similarly reduced, the invention provides a cell design on the silicon level in which a transistor is adjacent a trench capacitor and formed in conventional seam-free single crystal silicon using a smaller Appeal No. 1998-3078 Page 3 Application No. 08/365,617 area on the silicon level than the conventional cell. The invention further provides a segment gate and spacer word line integrated with this smaller silicon level cell design to reduce the area of the whole cell. In summary, the invention provides a structure having a reduced cell area because of reductions in area on both levels while providing the transistor in conventional seam-free single crystal semiconductor. Claim 1, which is representative for our purposes, follows: 1. A semiconductor structure, comprising a device having a gate, said gate consisting of an individual segment of gate conductor on a thin gate dielectric, said device further comprising a seam-free single crystal semiconductor substrate; and a connector on top of and electrically contacting said segment gate conductor, said connector being a conductive spacer rail extending beyond said device. The references relied on in rejecting the claims follow: Dhong et al. (Dhong) 5,214,603 May 25, 1993 Appeal No. 1998-3078 Page 4 Application No. 08/365,617 Hayden 5,498,889 Mar. 12, 1996 (filed Dec. 12, 1994). Claims 1-15, 24, and 26-28 stand rejected under 35 U.S.C. § 103 as obvious over Dhong in view of Hayden. Rather than repeat the arguments of the appellant or examiner in toto, we refer the reader to the briefs and answer for the respective details thereof. OPINION In deciding this appeal, we considered the subject matter on appeal and the rejection advanced by the examiner. Furthermore, we duly considered the arguments and evidence of the appellant and examiner. After considering the totality of the record, we are persuaded that the examiner erred in rejecting claims 1-15, 24, and 26-28. Accordingly, we reverse. We begin by noting the following principles from In re Rijckaert, 9 F.3d 1531, 1532, 28 USPQ2d 1955, 1956 (Fed. Cir. 1993). Appeal No. 1998-3078 Page 5 Application No. 08/365,617 In rejecting claims under 35 U.S.C. Section 103, the examiner bears the initial burden of presenting a prima facie case of obviousness. In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992).... "A prima facie case of obviousness is established when the teachings from the prior art itself would appear to have suggested the claimed subject matter to a person of ordinary skill in the art." In re Bell, 991 F.2d 781, 782, 26 USPQ2d 1529, 1531 (Fed. Cir. 1993) (quoting In re Rinehart, 531 F.2d 1048, 1051, 189 USPQ 143, 147 (CCPA 1976)). With these principles in mind, we consider the examiner's rejection. Recognizing that Dhong does not teach a seam-free substrate, the examiner alleges, "[i]t would have been obvious to one skilled in this art to form Dhong et al's DRAM cell in a 'seam-free' single crystal semiconductor substrate as suggested by Hayden." (Examiner's Answer at 3) “Obviousness may not be established using hindsight or in view of the teachings or suggestions of the inventor.” Para-Ordnance Mfg., 73 F.3d at 1087, 37 USPQ2d at 1239 (citing W.L. Gore & Assocs., Inc., 721 F.2d at 1551, 1553, 220 USPQ at 311, 312-13 (Fed. Cir. 1983)). “It is impermissible to use the claimed invention as an instruction manual or ‘template’ Appeal No. 1998-3078 Page 6 Application No. 08/365,617 to piece together the teachings of the prior art so that the claimed invention is rendered obvious.” In re Fritch, 972 F.2d 1260, 1266, 23 USPQ2d 1780, 1784 (Fed. Cir. 1992) (citing In re Gordon, 733 F.2d 900, 902, 221 USPQ 1125, 1127 (Fed. Cir. 1984)). "[T]o establish obviousness based on a combination of the elements disclosed in the prior art, there must be some motivation, suggestion or teaching of the desirability of making the specific combination that was made by the applicant." In re Kotzab, 217 F.3d 1365, 1370, 55 USPQ2d 1313, 1316 (Fed. Cir. 2000) (citing In re Dance, 160 F.3d 1339, 1343, 48 USPQ2d 1635, 1637 (Fed. Cir. 1998) and In re Gordon, 733 F.2d 900, 902, 221 USPQ 1125, 1127 (Fed. Cir. 1984)). Here, the examiner fails to identify a sufficient reason to combine Hayden with the Dhong. He merely opines, "[i]t would have been obvious ... to form Dhong et al's DRAM cell in a 'seam-free' single crystal semiconductor substrate as suggested by Hayden." (Id.) Such a broad, conclusory opinion does not meet the requirement for some motivation, suggestion, or teaching of the desirability of making the combination. Appeal No. 1998-3078 Page 7 Application No. 08/365,617 Because there is no evidence that the Hayden's seam-free substrate would have been desirable in Dhong's DRAM cell, we are not persuaded that teachings from the prior art would have suggested the combination. Therefore, we reverse the rejection of claims 1-15, 24, and 26-28 as obvious over Dhong in view of Hayden. CONCLUSION In summary, the rejection of claims 1-15, 24, and 26-28 stand rejected under 35 U.S.C. § 103 as obvious over Dhong in view of Hayden is reversed. REVERSED Appeal No. 1998-3078 Page 8 Application No. 08/365,617 KENNETH W. HAIRSTON ) Administrative Patent Judge ) ) ) ) ) BOARD OF PATENT LANCE LEONARD BARRY ) APPEALS Administrative Patent Judge ) AND ) INTERFERENCES ) ) ) STUART S. LEVY ) Administrative Patent Judge ) LLB/kis JAMES M. LEAS IBM CORPORATION DEPT. 915/BLDG. 972-2 INTELLECTUAL PROPERTY LAW 1000 RIVER STREET ESSEX JUNCTION, VT 05452 Copy with citationCopy as parenthetical citation