Ex Parte Nishio et al

Board of Patent Appeals and Interferences

May 31, 2011

10902032 (B.P.A.I. May. 31, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/902,032 07/30/2004 Ryoji Nishio 648.44122X00 3063
20457 7590 05/31/2011
ANTONELLI, TERRY, STOUT & KRAUS, LLP
1300 NORTH SEVENTEENTH STREET
SUITE 1800
ARLINGTON, VA 22209-3873
EXAMINER
MACARTHUR, SYLVIA
ART UNIT PAPER NUMBER
1716
MAIL DATE DELIVERY MODE
05/31/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________

Ex parte RYOJI NISHIO,
TADAMITSU KANEKIYO, YOSHIYUKI OOTA,
and TSUYOSHI MATSUMOTO

__________

Appeal 2010-007419
Application 10/902,032
Technology Center 1700
___________

Before ADRIENE LEPIANE HANLON, LINDA M. GAUDETTE, and
KAREN M. HASTINGS, Administrative Patent Judges.

HANLON, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-007419
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A. STATEMENT OF THE CASE
This is a decision on appeal under 35 U.S.C. § 134 from an Examiner’s
decision finally rejecting claims 1 and 4-8, all of the pending claims.1 We have
jurisdiction under 35 U.S.C. § 6(b).2
We REVERSE and enter a new ground of rejection.
The subject matter on appeal relates to a plasma processing apparatus.
Claim 1, reproduced below, is illustrative.
1. A plasma processing apparatus for processing an object to be
processed using plasma, the apparatus comprising:
a process stage for placing the object to be processed; and
a focus ring disposed on the process stage surrounding the
object to be processed, the focus ring and the object to be processed
being subjected to application of RF bias;
wherein the plasma apparatus further comprises equivalent
circuit analysis means that includes an equivalent circuit modeling of
plasma and ion sheath based on a plasma sheath model, simultaneous
analysis of a plasma load on the object to be processed in the ion
sheath based on the plasma sheath model and a plasma load on the
focus ring, and setting of the capacitance between the focus ring and
the process stage to a value flattening an equi-potential surface within
the ion sheath.
App. Br., Claims Appendix (emphasis added).3
The Appellants seek review of the following Examiner’s rejections:
a) the rejection of claims 1 and 4-8 under 35 U.S.C. § 102(b) as
anticipated by Hasegawa4; and

1 Claims 2, 3, and 9-18 were cancelled in an amendment dated March 27,
2007.
2 An oral hearing was held on May 11, 2011.
3 Appeal Brief dated January 15, 2008.
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b) the rejection of claims 1 and 4-8 under 35 U.S.C. § 103(a) as
unpatentable over the combination of Hasegawa, Yassine,5 and Thévenin’s
theorem.6,7
B. DISCUSSION
1. Rejection under § 103(a)
At the outset, we note that claim 1 recites an “equivalent circuit analysis
means.” The Examiner appears to have interpreted this limitation as invoking
§112, sixth paragraph,8 and has identified the means as “a controller that is [a]
process analyzer or computer with an algorithm that provides the steps as claimed
such as modeling the plasma/ion sheath, analysis of plasma load, and setting the
capacitance as recited in claim 1.” Final 2.
The Examiner finds that Hasegawa does not teach an equivalent circuit
analysis means and thus, does not teach a means that includes the three steps
recited in claim 1, i.e., the equivalent circuit modeling step, the simultaneous
analysis step, and the capacitance setting step. Ans. 4.
The Examiner finds that Yassine teaches the use of equivalent circuit
analysis to analyze a semiconductor device and perform process control based on

4 US 5,556,500 issued September 17, 1996.
5 US 6,465,266 B1 issued October 15, 2002.
6 Wikipedia (2003), available at
http://en.wikipedia.org/wicki/Th%C3%A9venin’s_theorem.
7 In the Final Office Action dated June 13, 2007 (“Final”), claims 1 and 4-8
were also rejected under 35 U.S.C. § 112, second paragraph; 35 U.S.C. § 112, first
paragraph, based on enablement; and 35 U.S.C. § 101. These rejections were
withdrawn in the Examiner’s Answer dated May 6, 2009 (“Ans.”), at 2-3.
8 At the oral argument, the Appellants’ representative also indicated that the
“equivalent circuit analysis means” recited in claim 1 invokes § 112, sixth
paragraph. Tr. 2:16-20.
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the analysis. Ans. 4. The Examiner also finds that the excerpt on Thévenin’s
theorem defines equivalent circuit analysis and the parameters used in such an
analysis. Ans. 6.
The Examiner contends that the steps of analysis performed by the claimed
analyzer are interpreted “as optimization steps as each individually or collectively
work to optimize the process parameters of the treatment process and ensure the
desired product result.” Ans. 5. The Examiner concludes that it would have been
obvious to one of ordinary skill in the art to combine the teachings of the prior art
of record “to provide a plasma apparatus to use an ECA [(equivalent circuit
analysis)] means to optimize the process parameters such as the capacitance
between the focus ring and the process stage to ensure a desired plasma processing
result.” Ans. 5.
The Appellants argue that the prior art of record does not disclose or suggest
all of the features recited in claim 1. App. Br. 14. In particular, the Appellants
contend that they “have applied equivalent circuit analysis as a component of a
plasma processing apparatus in order to set the capacitance between the focus ring
and the process stage to a value which flattens the equi-potential surface within the
ion sheath.” App. Br. 15. The Appellants argue that the prior art of record does
not disclose or suggest this feature. App. Br. 15.
The Appellants’ position is supported by the record. In particular, the
Examiner has failed to direct us to any disclosure in the prior art of record of an
equivalent circuit analysis means that performs the steps recited in claim 1. Thus,
any optimization of these steps cannot be said to have been obvious to one of
ordinary skill in the art. For this reason, the § 103(a) rejection on appeal will be
reversed.
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2. Rejection under § 102(b)
The Examiner does not address the § 102(b) rejection in the Answer.
Moreover, the Examiner finds that “Hasegawa et al fails to teach an equivalent
circuit analysis means and consequently fails to teach a means that includes the
three steps recited in claim 1: an equivalent circuit modeling, simultaneous
analysis, and setting of the capacitance between the focus ring and the process
stage.” Ans. 4. Thus, the § 102(b) rejection on appeal will also be reversed. See
In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997) (“To anticipate a claim, a
prior art reference must disclose every limitation of the claimed invention, either
explicitly or inherently.”).
C. NEW GROUND OF REJECTION
The Examiner contends that “claims 1-6 [sic, claims 1 and 4-8] overlap two
statutory classes of inventions, namely apparatus and method.” Final 2.
We agree. Claim 1 is directed to “[a] plasma processing apparatus.” The
first three elements of the claim are apparatus elements, i.e., a process stage, a
focus ring, and “equivalent circuit analysis means.” As discussed above, both the
Examiner and the Appellants take the position that the “equivalent circuit analysis
means” invokes § 112, sixth paragraph. However, claim 1 does not use the phrase
“means for” followed by corresponding function for the “equivalent circuit
analysis means.” Instead, claim 1 recites that the “equivalent circuit analysis
means” includes the steps of modeling, analysis, and setting:
wherein the plasma apparatus further comprises equivalent
circuit analysis means that includes [1] an equivalent circuit modeling
of plasma and ion sheath based on a plasma sheath model, [2]
simultaneous analysis of a plasma load on the object to be processed
in the ion sheath based on the plasma sheath model and a plasma load
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on the focus ring, and [3] setting of the capacitance between the focus
ring and the process stage to a value flattening an equi-potential
surface within the ion sheath.
App. Br., Claims Appendix (emphasis added).
We conclude that “equivalent circuit analysis means” does not invoke § 112,
sixth paragraph. See Sage Prods., Inc. v. Devon Indus., Inc., 126 F.3d 1420, 1427
(Fed. Cir. 1997) (“where a claim uses the word ‘means,’ but specifies no
corresponding function for the ‘means,’ it does not implicate section 112”).
Instead, we conclude that the steps of modeling, analysis, and setting recited in
claim 1 are method steps for using the claimed apparatus, and more specifically,
method steps for using the claimed equivalent circuit analysis means. Thus, claim
1 and claims 4-8, which depend from claim 1, are indefinite under 35 U.S.C. § 112,
second paragraph. Rembrandt Data Tech., LP v. AOL, LLC, 98 U.S.P.Q.2d 1393,
1400 (Fed. Cir. 2011) (indicating that claims reciting both an apparatus and a
method for using the apparatus are indefinite under § 112, second paragraph).9
D. DECISION
The rejection of claims 1 and 4-8 under 35 U.S.C. § 102(b) as anticipated by
Hasegawa is reversed.
The rejection of claims 1 and 4-8 under 35 U.S.C. § 103(a) as unpatentable
over the combination of Hasegawa, Yassine, and Thévenin’s theorem is reversed.
Claims 1 and 4-8 are rejected under 35 U.S.C. § 112, second paragraph, as
failing to particularly point out and distinctly claim the subject matter which the

9 In the event that further prosecution results in amending claim 1 to recite
an “equivalent circuit analysis means for” modeling, analysis, and setting, the
Examiner should determine whether the original disclosure describes the necessary
algorithms for performing these functions.
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Applicants regard as their invention. This is a new ground of rejection pursuant to
37 C.F.R. § 41.50(b) (effective September 13, 2004, 69 Fed. Reg. 49960 (August
12, 2004), 1286 Off. Gaz. Pat. Office 21 (September 7, 2004)).
37 C.F.R. § 41.50(b) provides that “[a] new ground of rejection pursuant to
this paragraph shall not be considered final for judicial review.” 37 C.F.R.
§ 41.50(b) also provides that the Appellants, WITHIN TWO MONTHS FROM
THE DATE OF THE DECISION, must exercise one of the following two options
with respect to the new ground of rejection to avoid termination of the appeal as to
the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the examiner, in
which event the proceeding will be remanded to the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .

REVERSED;
37 C.F.R. § 41.50(b)

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