Ex Parte Nishihara

Patent Trial and Appeal Board

Mar 28, 2014

11493904 (P.T.A.B. Mar. 28, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte TOSHIYUKI NISHIHARA
____________________

Appeal 2011-011670
Application 11/493,9041
Technology Center 2100
____________________

Before JAMES R. HUGHES, MICHAEL J. STRAUSS, and
J. JOHN LEE, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed July 27, 2006, claiming priority to Japanese Patent
Application Nos. JP 2005-221714, filed July 29, 2005 and JP 2006-137844,
filed May 17, 2006. The real party in interest is Sony Corp.
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STATEMENT OF THE CASE
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s final decision rejecting claims 1, 2, 4-16, and 18-27. Claims 3,
17, and 28-30 have been canceled (App. Br. 2.)2 We have jurisdiction under
35 U.S.C. § 6(b). An Oral Hearing was held on February 25, 2014.
We affirm.
Appellant’s Invention
The invention at issue on appeal relates to storage devices and
computer systems including a control unit that interrupts a restoration
process, stores data (the progress of the restoration process and a location of
an erasure block), and sets a flag. (Spec. 1:12-16; 14:7-19:14; Abstract.)
Representative Claim
Independent claim 1, reproduced below, with disputed limitations
italicized, further illustrates the invention:
1. A storage device comprising:
a flash memory as a main storage and further comprising
original data stored in an original region, and
a control unit,
wherein the control unit rewrites at least a partial region
of the original region in the flash memory by writing update
data to an empty region in addition to restoring an invalidated
region of the original region and when access occurs to data
stored in the storage device from an external source while a
restoration processing is underway, the control unit interrupts
said restoration processing, stores a state of progress in a

2 We refer to Appellant’s Specification (“Spec.”); Appeal Brief (“App. Br.”)
filed January 27, 2011; and Reply Brief (“Reply Br.”) filed June 9, 2011.
We also refer to the Examiner’s Answer (“Ans.”) mailed April 12, 2011.
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memory or register, stores a location of an erasure block to be
restored as progress information, sets a flag indicating that the
restoration processing was interrupted, and performs
processing to respond to the access,
wherein when the processing to respond to the access is
completed, the restoration processing is executed from the
location of the erasure block; and
automatically restores the invalidated region of the
original region as another empty region by erasing the original
region at a time of standby of the storage device with no access
from outside as the restoration processing.
Rejections on Appeal
1. The Examiner rejects claims 1, 2, 4, 7-11, 14, 22-24, and 27
under 35 U.S.C. § 103(a) as being unpatentable over U.S. Patent No.
5,933,847, issued Aug. 3,1999 (“Ogawa”) and U.S. Patent No. 6,552,956
B2, issued Apr. 22, 2003 (“Shibata”).
2. The Examiner rejects claims 5, 6, 12, 13, 25, and 26 under
35 U.S.C. § 103(a) as being unpatentable over Ogawa, Shibata, and U.S.
Patent No. 6,484,270 B1, issued Nov. 19, 2002 (“Odani”).
3. The Examiner rejects claims 15, 16, and 18 under 35 U.S.C.
§ 103(a) as being unpatentable over Ogawa, Shibata, and U.S. Patent App.
Pub. No. 2006/0221704 A1, published Oct. 5, 2006 (filed Apr. 1, 2005)
(“Li”).
4. The Examiner rejects claims 19-21 under 35 U.S.C. § 103(a) as
being unpatentable over Ogawa, Shibata, Odani and Li.

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ISSUES
Based on our review of the administrative record, Appellant’s
contentions, and the Examiner’s findings and conclusions, the pivotal issues
before us follow:
1. Does the Examiner err in concluding that the combination of
Ogawa and Shibata collectively teaches or suggests
when access occurs . . . the control unit interrupts said
restoration processing, stores a state of progress in a memory or
register, stores a location of an erasure block to be restored as
progress information, sets a flag indicating that the restoration
processing was interrupted, and performs processing to respond
to the access
within the meaning of claim 1 and the commensurate limitations of claim 9?
2. Does the Examiner err in concluding that the combination of
Ogawa, Shibata, and Li collectively teaches or suggests
wherein the control unit performs at least a portion of a
processing for restoring the invalidated region from said empty
region in parallel with a term where access from outside hits the
cache memory and the cache is accessed during the restoration
processing
when access occurs . . . the control unit interrupts said
restoration processing, stores a state of progress in a memory or
register, stores a location of an erasure block to be restored as
progress information, sets a flag indicating that the restoration
processing was interrupted, and performs processing to respond
to the access, and
wherein, when access from the outside misses the cache
memory and the restoration processing is underway, the control
unit interrupts the restoration processing and performs
processing to respond to the access
as recited in claim 15?

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FINDINGS OF FACT
We adopt the Examiner’s findings in the Answer and the Final Office
Action mailed August 3, 2010 as our own, except as to those findings that
we expressly overturn or set aside in the Analysis that follows.

ANALYSIS
Rejection of Claims 1, 4, 7, 9, 11, 22, and 24
Appellant contends that the combination of Ogawa and Shibata does
not teach the disputed features of Appellant’s independent claim 1. (App.
Br. 22-26; Reply Br. 3-8.) Specifically, Appellant contends that Ogawa does
not teach interrupting a restoration process due to an external source
accessing stored data – “when access occurs to data stored in the storage
device from an external source while a restoration processing is underway,
the control unit interrupts said restoration processing” (Claim 1). Appellant
also contends that Shibata does not teach storing a state of progress, an erase
block location, or setting a flag (indicator) – that “the control unit . . . stores
a state of progress in a memory or register, stores a location of an erasure
block to be restored as progress information, sets a flag indicating that the
restoration processing was interrupted” (claim 1). (Id.)
The Examiner sets forth a detailed explanation of the obviousness
rejection in the Examiner’s Answer with respect to each of the claims (Ans.
3-26), and in particular claim 1 (Ans. 3-5; 21-23). Specifically, the
Examiner explains that Shibata describes interrupting a burst erase
operation, storing a burst value (number of remaining erase operations) (i.e.,
the state of progress), storing the current address of the erase operation, and
setting a mode signal (i.e., setting a flag or indicator). (Ans. 4-5; 21-23
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(citing Shibata, col. 3, ll. 10-30, 55-65; col. 8, ll. 15-35; col. 9, ll. 35-45; col.
14, ll. 45-65; col. 15, ll. 1-15).) We adopt these findings and this reasoning
as our own.
Based on Appellant’s arguments (App. Br. 22-26, 28-30, 32-33, 35-
36, 42-44, and 45-46), we select independent claim 1 as representative of
Appellant’s arguments and groupings with respect to claims 1, 4, 7, 9, 11,
22, and 24. 37 C.F.R. § 41.37(c)(1)(vii)(2004). Upon consideration of the
evidence on this record and each of Appellant’s contentions, we find that the
preponderance of evidence on this record supports the Examiner’s findings
and ultimate conclusion that Ogawa and Shibata teach or would have at least
suggested the disputed features of claim 1. Accordingly, we sustain the
Examiner’s rejection of claim 1 for the reasons set forth in the Answer,
which we incorporate herein by reference. (Ans. 3-5; 21-23.) Our
additional analysis will be limited to the following points of emphasis.
We initially note that the Examiner cited Shibata, not Ogawa, as
teaching interrupting the restoration process (Ans. 4-5, 21-23). Thus, we are
not persuaded by Appellant’s argument (supra), that Ogawa does not teach
this feature.
We further note that the argued portions of the disputed limitations –
“the control unit . . . stores a state of progress in a memory or register, stores
a location of an erasure block to be restored as progress information, sets a
flag indicating that the restoration processing was interrupted” (claim 1) –
consist of statements of intended use and non-functional descriptive material
that do not limit the recited “storage device,” “control unit,” and/or “memory
or register” of the storage device structurally or functionally. Specifically,
the statements of intend use – the control unit storing data and setting a flag
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(“stores a state of progress in a memory or register, stores a location of an
erasure block to be restored as progress information, sets a flag indicating
that the restoration processing was interrupted” (claim 1)) – in this instance
does not further limit the scope of the claim. See Boehringer Ingelheim
Vetmedica, Inc. v. Schering-Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir.
2003) (a statement of intended use “usually will not limit the scope of the
claim because such statements usually do no more than define a context in
which the invention operates”).
Further, the recited information or data to be stored – i.e., “state of
progress” and “location of an erasure block to be restored as progress
information” (claim 1) – are essentially non-functional descriptive material
in that these limitations simply require data be stored in memory. Therefore,
the functionality of “storing” the data remain the same regardless of what the
data constitutes or how the data may be named. The informational content
of the data, thus, represents non-functional descriptive material, which “does
not lend patentability to an otherwise unpatentable computer-implemented
product or process.” Ex parte Nehls, 88 USPQ2d 1883, 1889 (BPAI 2008)
(precedential). See Ex parte Curry, 84 USPQ2d 1272, 1274 (BPAI 2005)
(informative) (Fed. Cir. Appeal No. 2006-1003), aff’d, (Rule 36) (June 12,
2006) (“wellness-related” data in databases and communicated on
distributed network did not functionally change either the data storage
system or the communication system used in the claimed method); see also
In re Ngai, 367 F.3d 1336, 1339 (Fed. Cir. 2004); Nehls, 88 USPQ2d 1883,
1887-90 (BPAI 2008) (discussing non-functional descriptive material).
Moreover, the storing of data and setting of the flag need not even occur if
access does not occur (restoration is not interrupted). Thus, this step fails to
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narrow claim 1. See In re Johnston, 435 F.3d 1381, 1384 (Fed. Cir. 2006)
(“optional elements do not narrow the claim because they can always be
omitted”).
Even if we arguendo ascribe patentable weight to the statements of
intended use and non-functional descriptive material, as explained by the
Examiner, Shibata describes these disputed features of claim 1. (Ans. 4-5;
21-23.) Shibata describes interrupting an erase operation (col. 14, ll. 55-56
(“erase operation is interrupted”)). (See Ans. 4-5, 21-22; Shibata, col. 8, ll.
1-35; col. 14, ll. 45-65.) Shibata also describes storing and decrementing a
burst value (number of remaining erase operations), which teaches storing “a
state of progress” (claim 1). (See Ans. 4-5, 21-22; Shibata, col. 3, ll. 10-18;
col. 8, ll. 5-31; col. 9, ll. 36-41.) Shibata further describes storing the current
address of the erase operation, and setting a mode signal (i.e., setting a flag
or indicator). (See Ans. 4-5; 21-23; Shibata, col. 3, ll. 10-30, 55-65; col. 8,
ll. 1-15, 50-65; col. 14, ll. 45-65; col. 15, ll. 1-15). Therefore, we find that
Shibata describes each disputed features of Appellant’s claim 1, and we
conclude that Shibata, in combination with Ogawa, teaches or would have at
least suggested “the control unit . . . stores a state of progress in a memory or
register, stores a location of an erasure block to be restored as progress
information, sets a flag indicating that the restoration processing was
interrupted” (claim 1). We find Appellant’s contrary arguments unavailing.
Thus, Appellant does not persuade us of error in the Examiner’s obviousness
rejection of representative independent claim 1.
With respect to independent claims 9 and 22, Appellant simply
reiterates the arguments made with respect to claim 1. (See App. Br. 32-33,
42-44.) Therefore, for the same reasons as claim 1 (supra), we find
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Appellant’s arguments in connection with claim 9 to be unpersuasive of
Examiner error.
With respect to dependent claims 4 and 7, Appellant mischaracterizes
the Examiner’s rejection and argues that neither Ogawa nor Shibata teaches
interrupting the restoration process. (App. Br. 28-30.) These arguments
simply reiterate the arguments made with respect to claim 1 (supra). With
respect to claim 11 and claim 24, Appellant simply reiterates the arguments
made with respect to claim 4, which reiterate the arguments made with
respect to claim 1 (supra). (App. Br. 35-36, 45-46.) Therefore, for the same
reasons as claim 1 (supra), we find Appellant’s arguments in connection
with claims 4, 7, 11 and 24 to be unpersuasive of Examiner error.
Thus, Appellant does not persuade us of error in the Examiner’s
obviousness rejection of representative independent claim 1, independent
claims 9 and 22, and dependent claims 4, 7, 11, and 24 (dependent on claims
1, 7, and 22, respectively). Accordingly, we affirm the Examiner’s
obviousness rejections of claims 1, 4, 7, 9, 11, 22, and 24.
Rejection of Claims 2, 8, 10, 14, 23, and 27
Appellant contends that Ogawa and Shibata do not teach the disputed
features of claim 2. (App. Br. 26-28; Reply Br. 8-11.) Specifically,
Appellant contends that Ogawa does not teach a “‘flash memory has a
plurality of erasure blocks as block erasure units, each erasure block
including a plurality of page regions as write units independent from each
other’” (App. Br. 26 (quoting claim 2) (italics omitted)) and “‘the control
unit includes, as the restoration processing, backing up data of a valid page
region remaining in an erasure block including an invalid page region to be
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restored to an erased empty region of another erasure block’” (App. Br. 27
(quoting claim 2) (italics omitted)).
The Examiner explains that Ogawa teaches the disputed features of
Appellant’s claim 2. (Ans. 6, 23.) In particular, the Examiner finds Ogawa
teaches a plurality of erase blocks and independent sectors (page regions),
erasing (invalid) sectors, and backing up valid sectors to an erased sector.
(Ans. 6, 23 (citing Ogawa, col. 8, ll. 20-30; col. 9, ll. 10-25, 38-41; col. 10,
ll. 1-14; Figs. 4 and 8.) We adopt these findings and this reasoning as our
own. Accordingly, we sustain the Examiner’s rejection of claim 2 for the
reasons set forth in the Answer, which we incorporate herein by reference.
(Ans. 6, 23.) Our additional analysis will be limited to the following points
of emphasis.
As with claim 1 (supra), “backing up data of a valid page region
remaining in an erasure block including an invalid page region to be restored
to an erased empty region of another erasure block” (claim 2) consists of
non-functional descriptive material and statements of intended use that do
not limit the recited “storage device,” “control unit,” and “flash memory” of
the storage device structurally or functionally. Specifically, the functionality
of the control unit (what the control unit does – backing up data and erasing
data from particular page regions) are statements of intend use that do not
further limit the scope of the claim. See Boehringer Ingelheim Vetmedica,
320 F.3d at 1345.
Even if we arguendo ascribe patentable weight to the statements of
intended use, Ogawa describes the disputed features of claim 2, as explained
by the Examiner. (Ans. 6, 23.) Therefore, we find that Ogawa describes
each disputed features of Appellant’s claim 2, and we conclude that Shibata,
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in combination with Ogawa, teaches or would have at least suggested a flash
memory having “a plurality of erasure blocks as block erasure units, each
erasure block including a plurality of page regions as write units independent
from each other” (claim 2) and a control unit “backing up data of a valid
page region remaining in an erasure block including an invalid page region
to be restored to an erased empty region of another erasure block” (claim 2).
We find Appellant’s contrary arguments unpersuasive. Thus, Appellant
does not persuade us of error in the Examiner’s obviousness rejection of
claim 2 or claim 8, not separately argued with particularity (App. Br. 28).
With respect to claims 10 and 23, Appellant reiterates the arguments
made with respect to claim 2. Appellant and does not separately argue
claims 14 or 27 with particularity. (See App. Br. 33-35, 44-45.) Thus,
Appellant does not persuade us of error in the Examiner’s obviousness
rejection of claims 10, 14, 23, or 27. Accordingly, we affirm the Examiner’s
obviousness rejections of claims 2, 8, 10, 14, 23, and 27.
Rejection of Claims 5, 6, 12, 13, 25, and 26
The Examiner rejects claims 5, 6, 12, 13, 25, and 26 as being obvious
in view of Ogawa, Shibata, and Odani. (Ans. 13-16.) Appellant contends
that Odani does not cure the deficiencies of Ogawa and Shibata, and that
Odani do not teach the disputed features of claim 1 (supra) – i.e.,
interrupting restoration processing, storing a state of progress, storing an
erase block location, or setting a flag (indicator). Appellant does not
separately argue the limitations of claims 5 or 6. (App. Br. 30-31; Reply Br.
12-14.) Appellant reiterates these same arguments with respect to claims 12,
13, 25, and 26. (App. Br. 36-37, 46-47.)
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The Examiner sets forth a detailed explanation of the obviousness
rejection in the Examiner’s Answer with respect to each of claims 5, 6, 12,
13, 25, and 26. (Ans. 13-16, 25.) We adopt these findings and this
reasoning as our own. Appellant does not address the Examiner’s findings
or conclusions with respect to claims 5, 6, 12, 13, 25, and 26. Accordingly,
we sustain the Examiner’s rejection of claims 5, 6, 12, 13, 25, and 26 for the
reasons set forth in the Answer, which we incorporate herein by reference.
(Ans. 13-16, 25.)
As we explain with respect to claim 1 (supra), the combination of
Ogawa and Shibata teaches or suggests the features of claim 1 that Appellant
reargues with respect to claims 5, 6, 12, 13, 25, and 26. Thus, we find
Appellant’s contrary arguments unavailing. Accordingly, we affirm the
Examiner’s obviousness rejections of claims 5, 6, 12, 13, 25, and 26.
Rejection of Claim 15
Appellant contends that Ogawa, Shibata, and Li do not teach the
disputed features of claim 15. (App. Br. 37-39; Reply Br. 19-22.)
Specifically, Appellant reiterates the arguments made with respect to claim 1
(supra), and further contends that Li does not teach “‘wherein the control
unit performs at least a portion of a processing for restoring the invalidated
region from said empty region in parallel with a term where access from
outside hits the cache memory and the cache is accessed during the
restoration processing’” (App. Br. 39 (quoting claim 15) (italics omitted)).
The Examiner explains that Li, in combination with Ogawa and
Shibata, teaches the disputed features of Appellant’s claim 15. (Ans. 16-19,
25-26.) In particular, the Examiner submits that Li teaches parallel
restoration processing in that Li discloses “cache operations . . . that allow
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data to be transferred in or out of a memory while the internal memory
engaged in another operation, such as . . . erase” (Ans. 26 (quoting Li, ¶
[0043]). (See Ans. 17, 25-26 (citing Li, ¶¶ [0043], [0044]).) We adopt these
findings and this reasoning as our own. Accordingly, we sustain the
Examiner’s rejection of claim 15 for the reasons set forth in the Answer,
which we incorporate herein by reference. (Ans. 16-19, 25-26.) Our
additional analysis will be limited to the following points of emphasis.
As explained with respect to claim 1 (supra), the combination of
Ogawa and Shibata teaches interrupting restoration processing, storing a
state of progress, storing an erase block location, or setting a flag (indicator).
We find Appellant’s arguments directed to these features unavailing.
Appellant further contends that Li does not teach parallel restoration
processing – “wherein the control unit performs at least a portion of a
processing for restoring the invalidated region from said empty region in
parallel with a term where access from outside hits the cache memory and
the cache is accessed during the restoration processing” (claim 15). (App.
Br. 39.) Appellant summarizes Li, cites to Li’s paragraph [0045], and
explains that Li doesn’t mention the disputed feature. (Id.) Appellant,
however, does not address the Examiner’s basis for the rejection (Ans. 16-
19, 25-26), Li’s paragraphs [0043] and [0044]. We agree with the Examiner
that paragraph [0043] of Li describes accessing a cache during a memory
read, write, or erase operation and performing processing of the operation
during the accessing of the cache. Thus, we conclude that Li teaches or at
least would have suggested the disputed parallel restoration processing
feature of Appellant’s claim 15. We find Appellant’s contrary arguments
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unpersuasive of Examiner error. Accordingly, we affirm the Examiner’s
obviousness rejection of claim 15.
Rejection of Claims 16 and 18-21
With respect to claim 16, Appellant reiterates the arguments made
with respect to claim 4 (supra), which we found unpersuasive of Examiner
error. Appellant does not separately argue claim 18 with particularity.
(App. Br. 40-41.) With respect to claims 19-21, Appellant reiterates the
arguments made with respect to claim 5 (supra), which we also found
unpersuasive of Examiner error. (App. Br. 41-42.) Thus, Appellant does
not persuade us of error in the Examiner’s obviousness rejection of claims
16 and 18-21. Accordingly, we affirm the Examiner’s obviousness
rejections of claims 16 and 18-21.

CONCLUSION
Appellant has not shown that the Examiner erred in rejecting claims 1,
2, 4-16, and 18-27 under 35 U.S.C. § 103(a).

DECISION
We affirm the Examiner’s rejections of claims 1, 2, 4-16, and 18-27.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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