Ex Parte Nikitin et al

Patent Trial and Appeal Board

Sep 26, 2016

12371029 (P.T.A.B. Sep. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/371,029 02/13/2009
25281 7590 09/28/2016
DICKE, BILLIG & CZAJA
FIFTH STREET TOWERS
100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS, MN 55402
FIRST NAMED INVENTOR
Ivan Nikitin
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
I560.251.101/2008P51812US 6801
EXAMINER
SALERNO, SARAH KATE
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
09/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
USPTO.PA TENTS@dbclaw.com
dmorris@dbclaw.com
DBCLA W-Docket@dbclaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte IV AN NIKITIN,
JOACHIM MAHLER,
and THOMAS BEHRENS
Appeal2015-005319
Application 12/371,029
Technology Center 2800
Before ADRIENE LEPIANE HANLON, PETER F. KRATZ, and
DEBRA L. DENNETT, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellants filed an appeal under 35 U.S.C. § 134 from an Examiner's
decision finally rejecting claims 1---6. Claims 7-26 are also pending but have been
withdrawn from consideration. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
Independent claim 1 is reproduced below from the Claims Appendix of the
Appeal Brief dated December 16, 2014 ("App. Br."). The limitation at issue is
italicized.
1. A semiconductor device comprising:
Appeal2015-005319
Application 12/371,029
a first chip coupled to an electrical insulator; and
a sintered heat conducting layer disposed between the electrical
insulator and the first chip, a first surface of the sintered heat
conducting layer directly contacting a surface of the first chip, and a
second surface of the sintered heat conducting layer directly
contacting an electrically insulating surface of the electrical insulator,
wherein the surface of the first chip is completely covered by
the first surface of the sintered heat conducting layer.
App. Br. 11.
The claims on appeal stand rejected as follows:
(1) claims 1, 2, 5, and 6 under 35 U.S.C. § 103(a) as unpatentable over
Roh et al. 1 in view of Ide et al.; 2, 3
(2) claim 3 under 35 U.S.C. § 103(a) as unpatentable over Roh in view of
Ide and further in view of Morgan et al.; 4 and
(3) claim 4 under 35 U.S.C. § 103(a) as unpatentable over Roh in view of
Ide and further in view of Schwarzbauer. 5
1 US 2007/0018191 Al, published January 25, 2007 ("Roh").
2 US 2008/0160183 Al, published July 3, 2008 ("Ide").
3 The Examiner does not include claims 2, 5, and 6 in the statement of the rejection
in either the Final Office Action or the Examiner's Answer but addresses claims 2,
5, and 6 in the body of the rejection in both the Final Office Action and the
Examiner's Answer. See Final Office Action dated June 16, 2014 ("Final"), at 2-
3; Examiner's Answer dated March 2, 2015 ("Ans."), at 2-3. Thus, it is clear that
claims 2, 5, and 6 also stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Roh in view of Ide. See App. Br. 5 (stating that claims 1, 2, 5, and 6 stand
rejected under 35 U.S.C. § 103(a) based on Roh in view of and Ide). The
statement of the rejection has been corrected to include claims 2, 5, and 6.
4 US 5,138,177 A, issued August 11, 1992 ("Morgan").
5 US 5,654,586 A, issued August 5, 1997 ("Schwarzbauer").
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Application 12/371,029
B. DISCUSSION
Referring to Roh Figure 5, reproduced below, the Examiner finds Roh
discloses a semiconductor device comprising first chip 102 coupled to electrical
insulator 110 and heat conducting layer 112 disposed between the electrical
insulator and the first chip. Ans. 2. The Examiner finds a first surface of heat
conducting layer 112 directly contacts a surface of first chip 102. Ans. 2.
Roh Figure 5 is a cross-sectional view of a side view light emitting
diode (LED) according to an embodiment of the invention.
According to the method disclosed in Roh, first metal layer 112 and second
metal layer 114 are formed on first insulating substrate 110. Roh i-f 52. An
adhesive is applied onto first and second areas 114a and 114b of second metal
layer 114, allowing first substrate 110 to be attached to second substrate 140. Roh
i-f 55. An adhesive is also applied to a third substrate (i.e., wall part 120), and the
substrate is attached to first and second areas 112a and 112b of first metal layer
112. Roh i-f 56. Then, as shown in Roh Figure 8(e), "an LED chip 102 is mounted
on the first area 112a of the first metal layer" and LED chip 102 is connected to
first and second areas 112a and 112b of first metal layer 112 via wires 104. Roh
i-f 57 (emphasis added). Next, "a protective device 106 is mounted underneath the
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Application 12/371,029
first area 114a of the second metal layer and connected to the second area 114b of
the second metal layer via wires 104." Roh i-f 57 (emphasis added).
In a subsequent step, as shown in Roh Figure 8(j), "a transparent resin is
poured into the opened area adjoining the wall part 120 and cured to form a
transparent encapsulant 130 for encapsulating the LED chip 102." Roh i-f 58.
Resin is also "poured into the opened area 142 of the second substrate 140 and
cured to form an encapsulant 150 for encapsulating the protective device 106."
Roh i-f 58.
The Appellants argue that "some type of attachment material must be
between chip 102 and metal layer 112a for chip 102 to be mounted on metal layer
112a." App. Br. 6. For that reason, the Appellants argue "Roh fails to disclose a
first surface of the sintered heat conducting layer directly contacting a surface of
the first chip as recited by independent claim 1." App. Br. 6 (emphasis omitted).
In response, the Examiner finds "[t]he chip of Roh does not need to be
adhesively attached because the wire bonds and encapsulation will attach said chip
on the substrate." Ans. 5.
However, the Appellants argue:
Roh ... discloses that chip 102 is mounted on the first area 112a of
the first metal layer in the opened area 122. A protective device 106
is mounted underneath the first area 114a of the second metal
layer. ... [S]ince chip 102 and protective device 106 are on opposite
sides of substrate 110, gravity requires that chip 102 and protective
device 106 be fixed (i.e., mounted or flip-bonded) to the metal layers,
otherwise chip 102 and protective device 106 would not stay in place
for the subsequent wire bonding and/or encapsulation processes.
App. Br. 7. The Examiner does not respond to the Appellants' argument.
Claim 1 also recites that the heat conducting layer disposed between the
electrical insulator and the first chip be sintered. The Examiner finds Roh does not
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Application 12/371,029
teach that heat conducting layer 112 is a sintered layer. Nonetheless, the Examiner
finds Ide teaches that sintered conducting layers decrease manufacturing
temperature and time. The Examiner concludes that it would have been obvious to
one of ordinary skill in the art "to have modified the heat conducting layer taught
by Roh to be sintered because it reduces manufacturing temperature and time as
taught by Ide." Ans. 3 (citing Ide Abstract).
The Appellants argue that Ide "addresses the problem of thermal damage
when forming sintered layers." App. Br. 8. Therefore, the Appellants contend that
"[t]he reduction of manufacturing temperature and time for forming a sintered
layer is not a valid reason for replacing metal layer 112 of Roh (which is not a
sintered layer) with a sintered layer." App. Br. 8.
Significantly, Ide does not teach that sintering conducting layers decreases
the manufacturing temperature and time required to coat a substrate with a metal
layer, such as metal layer 112 of Roh. See Roh i-f 42 (disclosing that insulating
substrate 110 is coated with metal layers 112 and 114). Rather, Ide discloses that:
[T]he present invention provides a conductive sintered layer forming
composition and a conductive sintered layer forming method that
allow lowering of heating temperature and shortening of heating time
to be achieved in a process of accelerating sintering by heating to
[sic, the] metal nano-particle coated with an organic substance.
Ide i-f 10 (emphasis added). The invention disclosed in Ide is said to lower heating
temperature and shorten heating time in such a sintering process "by using a
conductive sintered layer forming composition containing metal particles whose
surface is coated with an organic substance and whose grain size is 1 nm to 5 µm
and silver oxide particles." Ide i-f 12.
Roh's metal layer 112 is not a sintered layer. Therefore, the Examiner's
reason for replacing Roh's metal layer 112 with the sintered layer disclosed in Ide
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is not supported by the record. See In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)
("there must be some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness" (emphasis added)).
For the reasons set forth above, the§ 103(a) rejection of independent claim 1
and dependent claims 2, 5, and 6 is not sustained.
The Examiner's reliance on Morgan and Schwarzbauer in the§ 103(a)
rejections of claims 3 and 4, respectively, does not cure the deficiencies in the
§ 103(a) rejection of claim 1 identified above. Therefore, the§ 103(a) rejections of
claims 3 and 4 are not sustained.
C. DECISION
The Examiner's decision is reversed.
REVERSED
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