Ex Parte Nickolls et al

Patent Trial and Appeal Board

Feb 22, 2016

13485622 (P.T.A.B. Feb. 22, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/485,622 05/31/2012
102324 7590 02/24/2016
Artegis Law Group, LLP/NVIDIA
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
FIRST NAMED INVENTOR
John R. Nickolls
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
NVDA/SC-08-0105-US 1-CONl 4079
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
02/24/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
kcruz@artegislaw.com
ALGdocketing@artegislaw.com
mmccauley@artegislaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JOHN R. NICKOLLS, LARS NYLAND, PETER C. MILLS,
JEREMY SUGERMAN, TIMOTHY FOLEY, BRIAN FAHS,
MICHAEL GARLAND, and DAVID P. LUEBKE
Appeal2014-004612
Application 13/485,622 1
Technology Center 2100
Before ST. JOHN COURTENAY III, CATHERINE SHIANG, and
TERRENCE W. McMILLIN, Administrative Patent Judges.
McMILLIN, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision2 on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1-16 and 18-20. Final Act. 1.3 We have jurisdiction
under 35 U.S.C. § 6(b ).
We affirm.
1 According to Appellants, the real party in interest is NVIDIA Corporation.
App. Br. 3.
2 Our decision refers to the Final Office Action mailed February 11, 2013
("Final Act."); Appellants' Appeal Brief filed September 23, 2013 ("App.
Br."); the Examiner's Answer mailed December 20, 2013 ("Ans.");
Appellants' Reply Brief filed February 21, 2014 ("Reply Br."); and the
Specification filed May 31, 2012 ("Spec.").
3 "Claim 17 is objected to as being dependent upon a rejected base claim"
and therefore, is not before us. Final Act. 2.
Appeal2014-004612
Application 13/485,622
REJECTIONS ON APPEAL
Claims 1, 2, 12, 13, and 18-20 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Wolfe et al. (US 2005/0278567 Al,
Dec. 15, 2005) ("Wolfe") and Matyas et al. (US 5,103,478, April 7, 1992)
("Matyas.") Final Act. 3.
Claims 3-11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wolfe, Matyas, and Schlansker et al. (US 6,023,751, Feb.
8, 2000) ("Schlansker.") Final Act. 7.
Claims 14--16 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wolfe, Matyas, and Smith et al. (US 4,967,347, Oct. 30,
1990) ("Smith.") Final Act. 10.
THE CLAIMED INVENTION
According to Appellants, "[ e ]mbodiments of the present invention
relate generally to parallel processing and more specifically to systems and
methods for voting among parallel threads." Spec. 2. Sole independent
claim 1 is directed to a method. Claim 1 recites (disputed limitation
highlighted):
A method for perfom1ing a vote operation for a group of
threads executing in parallel, the method comprising:
receiving a vote instruction that includes an opcode that
identifies the vote operation;
receiving a ballot of vote data that includes vote data
from each participating thread in the group of threads
executing in parallel within a core of a processing unit;
computing a vote result based on the ballot of vote data
according to the vote instruction; and
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Application 13/485,622
returning the vote result to the group of threads.
ANALYSIS
We have reviewed the rejections of claims 1-16 and 18-20 in light of
Appellants' arguments presented in the Appeal Brief and Reply Brief. We
are not persuaded that Appellants identify reversible error. We agree with
and adopt the Examiner's findings, reasoning, and conclusions as set forth in
the Final Action (Final Act. 3-14) and the Examiner's Answer (Ans. 2-7).
We highlight the following for emphasis.
Appellants argue that the cited art fails to teach or suggest, "receiving
a ballot of vote data that includes vote data from each participating thread,"
as recited in sole independent claim 1. App. Br. 9-11; Reply Br. 5.
Specifically, Appellants argue, "[t]he units in Wolfe that provide the outputs
are processors, rather than threads." App. Br. 9-10. In the Examiner's
Answer, the Examiner responds:
The Examiner disagrees for the following reasons. In the
appeal brief section "Summary of Claimed Subject Matter", the
appellant cites paragraph 59 for support of the claimed
limitation. This paragraph describes a vote instruction executed
on a processing engine as part of a thread. In figure 3 of the
drawings, a processing engine: a.) reads operands from the local
register file, b.) executes the Vote Instruction of a thread, and
c.) outputs and writes the execution result of the Vote
Instruction of the thread to the local register file. Afterwards,
the local register file directly provides the ballot of Vote data.
The thread executed within the processing engines output vote
data indirectly to the Vote Unit. Thus, the broadest reasonable
interpretation of the claimed limitation "receiving a ballot of
vote data that includes vote data from each participating thread
in the group of threads" is indirectly receiving Vote data from
threads executed.
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Application 13/485,622
The combination of Wolfe and ivfatyas shows processing
units 220-1to220-M (see figure 2 of Wolfe) executing
redundant threads. The execution of redundant threads on the
processing units output bits of vote data and send the vote data
to the hardware comparator (see Figure 2 element 230 of
Wolfe). A thread in isolation isn't capable of outputting vote
data. It's the execution of the thread on the processor that
allows the thread and instructions contained within the thread to
output their execution results. Thus the combination reads
upon the claimed limitation.
Ans. 2-3. The findings of the Examiner are well-supported by the cited art
and the reasoning and conclusion of the Examiner are reasonable.
Moreover, Appellants' argument is not commensurate with the scope
of the contested limitation. The disputed limitation does not recite that the
ballot of vote data is received from the threads. Claim 1 recites, "receiving a
ballot of vote data that includes vote data from each participating thread."
Appellants' argument does not take into account the words "that includes
vote data'' in the disputed limitation. The Examiner's interpretation of this
limitation and application of the teachings of the cited art are commensurate
with the broadest reasonable interpretation of the disputed limitation and
claim 1. We are not persuaded of error by this argument.
Appellants argue that the cited art fails to teach or suggest, "threads
executing in parallel within a core of a processing unit," as recited in claim
1. App. Br. 11-12. Specifically, Appellants argue, "the threads that
transmit vote data must be executing within a single core of a processor."
App. Br. 12. Appellants do not cite to any definition or disclaimer in the
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Application 13/485,622
Specification, or otherwise support this argument. App. Br. 11-12.4 The
Examiner cites Figure 2 and paragraph 18 of Wolfe as providing the relevant
teaching. Figure 2 of Wolfe is reproduced below:
Figure 2 of vVolfe depicts a programmable logic device (PLD) having
redundant processors. Wolfe ,-r 9. The Examiner's response to this argument
is: "PLD element 210 (see Wolfe Figure 2 and paragraph 18) is used to read
upon the core of the claimed limitation. The individual processors (see
Wolfe Figure 2 elements 220-1to220-M) on the PLD are used to read upon
4 An embodiment disclosed in the Specification depicts a parallel processing
unit (PPU) with multiple cores. See Spec., Figure 2, ref. nos. 208(0), 208(1)
... 208(C-1 ). The Specification states, "PPU 220 includes core 208 (or
multiple cores 208) configured to execute a large number of threads in
parallel." Spec. i-f34 (emphasis added). In Figures 3A and 3B, the PPU 220
is depicted as including multiple processing engines (Figure 3A, ref. nos.
302(0), 302(1) ... 302 (P-1 ); Figure 3B, ref. nos. 302(0), 302(1) ... 302
(7)).
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Application 13/485,622
the claimed processing units." Ans. 6. The Examiner's findings are
supported by the cited art and we see no error in mapping "a core of a
processing unit" as claimed to the PLD with multiple processors in Wolfe.
We are not persuaded of error by this argument.
For these reasons, we are not persuaded the Examiner erred in
rejecting sole independent claim 1 as obvious. Claims 2-16 and 18-20 are
not separately argued. Therefore, we affirm the rejections of claims 1-16
and 18-20.
DECISION
The rejections of claims 1-16 and 18-20 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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