Ex Parte Nguyen et al

Patent Trial and Appeal Board

May 17, 2018

14192048 (P.T.A.B. May. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/192,048 02/27/2014
51092 7590 05/21/2018
Eschweiler & Potashnik, LLC.
Rosetta Center
629 Euclid Ave., Suite 1000
Cleveland, OH 44114
FIRST NAMED INVENTOR
Dinh Quoc Thang Nguyen
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
KRAUP148US 1020
EXAMINER
ALHIJA, SAIF A
ART UNIT PAPER NUMBER
2128
NOTIFICATION DATE DELIVERY MODE
05/21/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@eschweilerlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DINH QUOC THANG NGUYEN, ANDREI DANIEL BASA,
and DIRK HAMMERSCHMIDT
Appeal2017-010054
Application 14/192,048 1
Technology Center 2100
Before ELENI MANTIS MERCADER, NORMAN H. BEAMER, and
ADAM J. PYONIN, Administrative Patent Judges.
BEAMER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1-20, which are all claims pending in the
application. (App. Br. 1.) We have jurisdiction over the pending rejected
claims under 35 U.S.C. § 6(b ).
We affirm.
1 Appellants identify Infineon Technologies AG as the real party in interest.
(App. Br. 1.)
Appeal2017-010054
Application 14/192,048
THE INVENTION
Appellants' disclosed and claimed invention is directed to emulation
of a coupling between a device under test and at least one further device.
(Abstract.) Independent claim 1, reproduced below, is illustrative of the
subject matter on appeal:
1. An emulation device, comprising:
a port configured to couple a device under test with the
emulation device, and
an emulator configured to emulate a plurality of different
possible properties of at least part of a physical wiring between
the device under test and at least one further device to test the
device under test under different physical wiring scenarios.
REJECTIONS
The Examiner rejected claims 1, 2, 4, 6, 8, and 17-20 under 35 U.S.C.
§ 103 as being unpatentable over Nemecek (US 7,099,818 Bl, issued Aug.
29, 2006) and Agarwal et al. (US 5,596,742, issued Jan. 21, 1997)
("Agarwal"). (Final Act. 2.)
The Examiner rejected claim 5 under 35 U.S.C. § 103 as being
unpatentable over Nemecek, Agarwal, and in view of Applicants' admitted
prior art ("AAP A"). (Final Act. 4.)
The Examiner rejected claims 7, 9, 10, and 13-16 under 35 U.S.C.
§ 103 as being unpatentable over Nemecek, Agarwal, and Genhong Ruan, A
Behavioral Model of AID Converters Using a Mixed-Mode Simulator, 26:3
IEEE JOURNAL OF SOLID-STATE CIRCUITS 283-90 (1991) ("Ruan"). (Final
Act. 4.)
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Application 14/192,048
The Examiner rejected claim 11 under 35 U.S.C. § 103 as being
unpatentable over Nemecek, Agarwal, Ruan, and in view of AAP A. (Final
Act. 7.)
The Examiner rejected claim 3 under 35 U.S.C. § 103 as being
unpatentable over Nemecek, Agarwal, and Alfred Fettweiss, Wave Digital
Filters: Theory and Practice, 74:2 PROCEEDINGS OF THE IEEE 270-327
(1986) ("Fettweiss"). (Final Act. 7 .)2
The Examiner rejected claim 12 under 35 U.S.C. § 103 as being
unpatentable over Nemecek, Agarwal, Ruan, and Fettweiss. (Final Act. 7 .)
ISSUE ON APPEAL
Appellants' arguments in the Appeal Brief present the following
dispositive issue: 3
Whether the Examiner erred in finding the combination of Nemecek
and Agarwal teaches or suggests the independent claim 1 limitation,
an emulator configured to emulate a plurality of different
possible properties of at least part of a physical wiring between
the device under test and at least one further device to test the
device under test under different physical wiring scenarios,
and the commensurate limitation of independent claims 9 and 17. (App. Br.
6-7.)
2 The heading of the rejection incorrectly omits the reference Agarwal,
whereas the body of the rejection refers to Agarwal. (See Final Act. 7.)
3 Rather than reiterate the arguments of Appellants and the positions of the
Examiner, we refer to the Appeal Brief (filed Jan. 23, 2017) (herein, "App.
Br."); the Final Office Action (mailed July 14, 2016) (herein, "Final Act.");
the Advisory Action (mailed Sept. 26, 2016) (herein, "Adv. Act."); and the
Examiner's Answer (mailed May 24, 2017) (herein, "Ans.") for the
respective details.
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Application 14/192,048
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner erred. We disagree with Appellants'
arguments, and we adopt as our own ( 1) the pertinent findings and reasons
set forth by the Examiner in the Action from which this appeal is taken
(Final Act. 2-9); (2) the pertinent findings and reasons set forth by the
Examiner in the Advisory Action (Adv. Act. 1-2); and (3) the corresponding
findings and reasons set forth by the Examiner in the Examiner's Answer in
response to Appellants' Appeal Brief. (Ans. 2-8.) We concur with the
applicable conclusions reached by the Examiner, and emphasize the
following.
In finding the combination of Nemecek and Agarwal teaches or
suggests the limitations of the claims at issue, the Examiner relies, inter alia,
on the disclosure in Nemecek of an in circuit emulator ("ICE") 210
containing a field programmable gate array ("FPGA") 214 with a circuit
under test inserted into pod 218 that may be capable of supporting various
device pin-outs. FPGA 214 is re-programmed every time the debugging
software 206 is run with pod 218 to program the ICE 210 to do something.
(Final Act. 3; Ans. 7-8; Nemecek 5:22--45, 7:58-8:21.)
The Examiner further relies on the disclosure of Agarwal of an
example of six logical wires allocated to six physical wires, followed by six
logical wires sharing a single physical wire using a combination of
pipelining and multiplexing, referred to as a "virtual interconnection."
(Final Act. 3 (emphasis omitted); Ans. 7-8; Agarwal 2:9-20, 4: 18-27, Figs.
2-3.)
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Appeal2017-010054
Application 14/192,048
Appellants argue that "Agarwal et al. do not teach or suggest different
physical wiring scenarios" (App. Br. 4) in which "Fig. 3 of Agarwal et al.
discloses a single wiring scenario" (App. Br. 4) and "[t]he emulation for a
system as in Fig. 2 of Agarwal emulates solely this one single physical
wiring scenario in which six physical wires connect between the two
devices with each of the six wires oriented the same way with the same
length." (App. Br. 5.) Appellants contend the disclosure provides the
meaning of the term "emulation" and specifies examples of different
properties of wiring. (App. Br. 5 (quoting Spec. i-fi-f 19, 26).)
We are not persuaded by these arguments. The Examiner finds, and
we agree, that (1) Nemecek "recites the emulation of connections between a
DUT and another device under different physical wiring scenarios" with
"multiple devices ... seen in the ICE and FPGA connected for testing", and
(2) Agarwal teaches "the concept of different virtual interconnections which
multiplexes different physical wires." (Ans. 7.) Here, the combination of
references teaches or suggests different physical wiring scenarios as
exemplified by the connections of one FPGA to another, in which physical
wirings are replaced in part by a single wire "used to provide signals which
correspond to the behavior of the actual coupling as close as possible" (Spec.
i-f 19), thereby "not only increas[ing] usable bandwidth, but also relax[ing]
the absolute limits imposed on gate utilization." (Agarwal 2:15-16.)
Appellants' argument that "[ c ]laim 1 recites that the emulation is with
regards to multiple, different properties of a physical wiring" (App. Br. 6) is
not commensurate with the scope of the claim, which requires "an emulator
configured to emulate a plurality of different possible properties of at least
part of a physical wiring" and is rendered obvious by an emulation of
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Appeal2017-010054
Application 14/192,048
physical wires by one wire carrying multiple signals, such as among
multiple PPG As, in which the timing of the signals emerging from one
FPGA must be adequately matched to the timing of the signals entering the
next FFPA. (See, e.g., Agarwal 5:56-6: 11.) Appellants' arguments in both
the Appeal and the Reply attack the references individually (see App. Br. 3-
7; Reply Br. 2--4), whereas the rejection is based on a combination of
references. In re Keller, 642 F.2d 413, 426 (CCPA 1981).
Accordingly, we sustain the Examiner's rejections of independent
claims 1, 9, and 17, and all dependent claims not separately argued with
particularity. (See App. Br. 6-8.)
CONCLUSION
We sustain the Examiner's rejection of claims 1, 2, 4, 6, 8, and 17-20
under 35 U.S.C. § 103 as being unpatentable over Nemecek and Agarwal.
We sustain the Examiner's rejection of claim 5 under 35 U.S.C. § 103
as being unpatentable over Nemecek, Agarwal, and in view of AAP A.
We sustain the Examiner's rejection of claims 7, 9, 10, and 13-16
under 35 U.S.C. § 103 as being unpatentable over Nemecek, Agarwal, and
Ruan.
We sustain the Examiner's rejection of claim 11 under 35 U.S.C.
§ 103 as being unpatentable over Nemecek, Agarwal, Ruan, and in view of
AAPA.
We sustain the Examiner's rejection of claim 3 under 35 U.S.C. § 103
as being unpatentable over Nemecek, Agarwal, and Fettweiss.
We sustain the Examiner's rejection of claim 12 under 35 U.S.C.
§ 103 as being unpatentable over Nemecek, Agarwal, Ruan, and Fettweiss.
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Application 14/192,048
DECISION
We affirm the Examiner's decision rejecting claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED
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