Ex Parte Negley et al

Patent Trial and Appeal Board

Mar 15, 2018

12017600 (P.T.A.B. Mar. 15, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/017,600 01/22/2008 Gerald H. NEGLEY 931078 6670
25191 7590 03/19/2018
BURR & BROWN, PLLC
PO BOX 7068
SYRACUSE, NY 13261-7068
EXAMINER
REAMES, MATTHEW L
ART UNIT PAPER NUMBER
2893
NOTIFICATION DATE DELIVERY MODE
03/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tpreston @burrandbrown.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GERALD H. NEGLEY and ANTONY PAUL VAN DE YEN
Appeal 2016-002222
Application 12/017,600
Technology Center 2800
Before MARK NAGUMO, WESLEY B. DERRICK, and
JENNIFER R. GUPTA, Administrative Patent Judges.
DERRICK, Administrative Patent Judge.
DECISION ON APPEAL1
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134 of the maintained
rejection of claims 1, 3—10, 12—16, 27, 28, 30, 42, 43, 45, 48, 49, 125—128,
130, and 131. We have jurisdiction under 35 U.S.C. § 6. We affirm-in-part
and enter new grounds of rejection pursuant to 37 C.F.R. § 41.50(b).
1 In our opinion, we refer to the Specification filed January 22, 2008
(“Spec.”), the Final Office Action issued November 24, 2014 (“Final Act.”),
the Appeal Brief filed June 29, 2015 (“Appeal Br.”), the Examiner’s Answer
issued October 22, 2015 (“Ans.”), and the Reply Brief filed December 15,
2015 (“Reply Br.”).
Appeal 2016-002222
Application 12/017,600
THE INVENTION
The claimed subject matter on appeal relates to a light emitter,
comprising light emitting devices mechanically interconnected by a common
substrate and an interconnection submount, in which the submount
electrically interconnects the light emitting devices, and to methods of
fabricating the light emitters. Spec. Abstract.
Independent claims 1,12, 27, and 42 are directed to light emitter
devices. Independent claims 30 and 125 are directed to methods of making
high voltage light emitter devices.
Independent claims 1 and 27 are representative.
1. A high voltage light emitter, comprising:
a plurality of light emitting devices on a substrate; and
an interconnection submount to which the plurality of
light emitting devices are electrically connected;
wherein the light emitting devices are electrically
interconnected by the interconnection submount to provide an
array of at least two serially connected subsets of light emitting
devices, each subset comprising at least three light emitting
devices electrically connected in parallel within the subset.
27. A high voltage light emitter, comprising:
a plurality of light emitting devices; and
means for electrically interconnecting the plurality of
light emitting devices to provide an array of at least two serially
connected subsets of light emitting devices, each subset
comprising at least three light emitting devices electrically
connected in parallel within the subset.
Appeal Br. (Claims App.) A-l, A-3.
Dependent claims 8 and 9, both depending from claim 7, which
depends from claim 1, are directed to light emitting devices comprising light
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Application 12/017,600
emitting diode devices isolated from one another by “at least one insulating
region” (claim 8) or “by at least one trench” (claim 9). Appeal Br. (Claims
App.) A-2.
THE REJECTIONS
Claims 8 and 9 stand rejected under 35U.S.C. § 112, second
paragraph (pre-AIA) for indefiniteness.
Claims 27, 28, 42, 43, 48, 49,2 and 130 stand rejected under 35 U.S.C.
§ 102(e) as anticipated by Fan ’893 or, in the alternative, under
35 U.S.C. § 103(a) as obvious over Fan ’89 in view of Ishizaka4
and Nishizawa.5
Claims 1, 3, 6—10, 12—16, 30, 125—128,6 and 131 stand rejected over
Fan ’89 in view of Nishizawa and Ishizaka.
Claims 4 and 5 stand rejected over Fan ’89 in view of Fee ’717 or
Fin.8
2 While not listed in the rejection headings, claim 49 is identified as rejected
and discussed in the body of the rejection. Final Act. 1, 8—9.
3 Fan et al., US 2006/0163589 Al, published July 27, 2006 (“Fan ’89”).
4 Ishizaka et al., US 2006/0171135 Al, published August 3, 2006
(“Ishizaka”).
5 Nishizawa et al., US 4,329,625, May 11, 1982 (“Nishizawa”).
6 Claim 128 is identified as rejected. Final Act. 1. Claim 128 is, however,
misidentified as nonexistant claim 135 in the articulated rejection of
claims 30 and 135 [sic, 128] that mirrors the related rejection of analogous
claims 12 and 127. Compare claims 12 and 30, with claims 127 and 128
(claims 127 and 128 add the same further limitation); compare Final
Act. 12—13, with id. at 14—15. Appellants do not contest this inadvertent,
harmless error. See generally Appeal Br.
7 Fee et al., US 2008/0017871 Al, published January 24, 2008 (“Fee ’71”);
the Examiner cites the reference in error as Fan ’71.
8 Fin et al., US 2008/0194054 Al, published August 14, 2008 (“Fin”).
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Claim 45 stands rejected over Fan ’89 in view of Lee ’16.9
DISCUSSION
For any ground of rejection, “the [Ejxaminer bears the initial burden
... of presenting a prima facie case of unpatentability.” In re Oetiker,
977 F.2d 1443, 1445 (Fed. Cir. 1992). We consider the record to determine
whether Appellants have identified reversible error in the Examiner’s
rejection. See In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (“[Ijthas
long been the Board’s practice to require an applicant to identify the alleged
error in the examiner’s rejections.” (citing Ex parte Frye, 94 USPQ2d 1072,
1075 (BPAI 2010) (precedential))). Further, “the burden of showing that the
error is harmful normally falls upon the party attacking the agency’s
determination.” In re Chapman, 595 F.3d 1330, 1338 (Fed. Cir. 2010)
(quoting Shinseki v. Sanders, 556 U.S. 396, 409 (2009)).
Upon consideration of the rejections, Appellants’ arguments, and the
Examiner’s response to those arguments, we reverse the indefiniteness
rejection of claims 8 and 9, the anticipation rejection of claims 27, 28, 42,
43, 48, 49, and 130, and the obviousness rejections of claims 4, 5, and 45.
We affirm the obviousness rejections of claims 27, 28, 42, 43, 48, 49, and
130 over Fan in view of Ishizaka and Nishizawa and of claims 1, 3, 6—10,
12—16, 30, 125—128, and 131 over these same references. We further enter
new grounds of rejection of claims 4 and 5, over Fan ’89 in view of Ishizaka,
Nishizawa, and Lin, and of claim 45 over Fan ’89 in view of Ishizaka,
Nishizawa, and Lee ’16.
9 Lee et al., WO 2007/001116 Al, published January 4, 2007 (“Lee ’16”).
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Indefiniteness
The Examiner maintains claims 8 and 9 are indefinite because they
recite that “the light emitting diode devices are isolated from one another,”
while claim 1, from which they ultimately depend, recites that the “plurality
of light emitting devices are electrically connected.” Ans. 3^4. The
Examiner’s reasons that the Specification “stat[ing] ‘that two or more
elements are “isolated” from each other means that the respective elements
are not electrically connected with each other (even though, for example,
they might both be in contact with another element)’” renders the claims
unclear because being “[electrically isolated means they are not connected
via anything.” Ans. 3^4.
A claim only fails to meet the statutory requirement that the claim be
definite if the language is ambiguous, vague, incoherent, opaque or
otherwise unclear in describing and defining the claimed invention. In re
Packard, 751 F.3d 1307, 1311 (Fed. Cir. 2014). Claims 8 and 9 are not such
claims that give rise to indefmiteness because it is clear that the light
emitting diodes that comprise the light emitting devices formed on the
substrate are isolated from one another “by at least one insulating region”
(claim 8) or “by at least one trench” (claim 9). Claim 1 requires that the
devices are electrically connected via the interconnection submount, and by
operation of law, a dependent claim must “be construed to incorporate by
reference all the limitations of the claim to which it refers.”
35 U.S.C. § 112, fourth paragraph (now § 112(d)). The Examiner erred
harmfully by expanding the scope of claims 8 and 9 beyond the scope of
claim 1 by requiring electrical isolation.
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We do not, accordingly, sustain the indefiniteness rejection of
claims 8 and 9.
Anticipation
The Examiner finds Fan ’89 anticipates claims 27, 28, 42, 43, 48, 49,
and 130 on the basis that the claims do not require “that within each subset
each of the at least three LED[s] are in parallel with one another or in
parallel with respective other LEDs.” Final Act. 4; see also id. at 7.
The Examiner erred reversibly because the anticipation rejection is
grounded on a meaning of parallel that is contrary to the plain meaning of
the term. See Rapoport v. Dement, 254 F.3d 1053, 1059 (Fed. Cir. 2001) (In
determining the meaning of the claims, we turn first to the claim itself.); see
also In re Suitco Surface, Inc., 603 F.3d 1255, 1259—60 (Fed. Cir. 2010).
The plain meaning of “at least three light emitting devices electrically
connected in parallel within the subset” (claim 27) requires that each of the
serially connected subsets contain at least three light emitting devices (e.g.,
LED) that are connected in parallel to one another. Put another way, there
are at least three parallel circuits within each subset and each of these
circuits comprise at least one light emitting device. This, the Examiner
finds, is lacking in Fan ’89. Final Act. 4, 7.
Because each of claims rejected as anticipated by Fan ’89 requires at
least three light emitting devices (or LEDs) in parallel, we reverse the
anticipation rejection of claims 27, 28, 42, 43, 48, 49, and 130.
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Obviousness
Fan ’89 in view of Ishizaka and Nishizawa
Claims 27, 28, 42, 42, 48, 49, and 120
In rejecting claim 27, the Examiner relies on Fan ’89 for its teaching
of a plurality of interconnected light emitting devices and means for
mechanically and electrically interconnecting the plurality of light emitting
devices to provide an array of at least two serially connected subsets of light
emitting devices. Final Act. 3 (citing Fan ’89, Figs. 7, 9). The Examiner,
thus, identifies the function of the means plus function limitation. The
Examiner also determines the corresponding structure in the Specification to
include the “wiring board with a substrate an[d] a[n] insulator” that is “the
same as Fan [’89]” such that “it is the same means for or at least equivalent.”
Final Act. 7—4.
As to “light emitting device,” the plain meaning of the phrase
encompasses devices comprising multiple light emitting diodes, as well as
further elements. “[W]e look to the specification to see if it provides a
definition for claim terms, but otherwise apply a broad interpretation.” In re
ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007). The
Specification sets forth that “[a]s used herein, the term Tight emitting
device’ refers to an individual light emitting structure (e.g., a light emitting
diode structure).” Spec. 37,11. 1—3. Individual light emitting structure is
not, however, further defined so as to limit its meaning to structures that
include only one light emitting element. The structure depicted in Figure 5
of the Specification, in which the individual light emitting structures are
individual FEDs, is, accordingly, merely an exemplified embodiment that
does not limit the claims. “[A]s applicants may amend claims to narrow
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their scope, a broad construction during prosecution creates no unfairness to
the applicant or patentee.” ICON Health, 496 F.3d at 1379.
The Examiner relies on Ishizaka and Nishizawa for their teaching of
multiple light emitting devices with the respective light emitting devices in
parallel. Final Act. 4. We understand, from the substance of the Examiner’s
discussion, that the teachings of Ishizaka and of Nishizawa are applied as
alternatives, rather than together—i.e., the “and” in the rejection should be
read as “or.” Ishizaka discloses multiple light emitting device subsets in
series in which each subset comprises more than three LEDs in parallel.
Ishizaka, Fig. 3. Nishizawa discloses plural light emitting device subsets
Sui—Sm in series in which each subset Sui comprises four series of light
emitting devices, each light emitting device comprising serial LEDs and a
resistor, arranged in parallel to one another. Ishizaka, Fig. 5A. The
Examiner further relies on Nishizawa for its disclosure of a rectifier allowing
alternating current to be used as an ultimate source of direct current in the
cited array. Ans. 5 (citing Nishizawa, Fig. 5A).
The Examiner concludes that one of ordinary skill in the art at the
time of the invention would have found it obvious to use multiple LEDs in
parallel as taught by Ishizaka and Nishizawa in order to gain redundancy so
that the subset would continue to function even if an LED bums out. Final
Act. 4.
The Examiner similarly relies on Fan ’89, Ishizaka, and Nishizawa in
rejecting independent claim 42, but relies further on Fan ’89 for its teaching
as to monolithic n-type and p-type layers forming LEDs. Final Act. 5—8.
As to claim 27, Appellants contend that Fan ’89 does not disclose
subsets of light emitting devices with at least three of the devices in parallel
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because what is disclosed are two series of devices in reverse parallel in
which current will flow through first series during approximately half the
AC cycle and will flow through the second series during the other half of the
AC cycle. Appeal Br. 36—37 (citing Fan ’89 23, 26, Figs. 5, 8, 9).
Appellants note that Ishizaka discloses light emitting apparatuses that
include a diode package having a plurality of LED chips mounted on a
substrate in parallel (Appeal Br. 39 (citing Ishizaka 132, Figs. 1, 2)) and a
light emitting apparatus having a plurality of similarly stmctured diode
packages connected in series {id. (citing Ishizaka ]Hf 44-45, Fig. 3)).
Appellants contend that “[t]he USPTO did not explain how it deems
that a person of ordinary skill in the art would modify the devices disclosed
in Fan [’89] in view of the disclosure in Ishizaka.” Appeal Br. 40.
Appellants also contend that any attempt to modify the LEDs in
Fan ’89, with LEDs in reverse parallel orientation, to be electrically
connected as in Ishizaka, with LEDs in parallel, would result in a device
incapable of performing the functions required by Fan ’89 because it would
not have one LED array turned on for approximately half an AC cycle and
another LED array turned on for the other half of the AC cycle. Appeal
Br. 40; see also Reply Br. 3—6.
Appellants note that Nishizawa discloses a device adapted for
operation by connection to an alternating current power supply that includes
a light emitting diode unit formed by a plurality of subunits connected in
series with each subunit comprising four unit circuits in parallel, each unit
circuit comprising, in series, a plurality of LEDs and a resistor. Appeal
Br. 41 (citing Nishizawa col. 14,1. 65—col. 15,1. 1, col 15,11. 14—20,
Fig. 5A).
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In the same manner as for Ishizaka, Appellants contend that “[t]he
USPTO did not explain how it deems that a person of ordinary skill in the art
would modify the devices disclosed in Fan [’89] in view of the disclosure in
Nishizawa” and that rearranging the LEDs in Fan ’89 would result in a
device incapable of performing the functions required by Fan ’89. Appeal
Br. 41; Reply Br. 6 (proffering similar arguments as to the Examiner’s
reliance on Nishizawa for a rectifier that allows alternating current to be
used as direct current).
As to claim 42, Appellants rely on the same arguments (Appeal
Br. 43 46; see also Reply Br. 6—8), but further contend that various
“benefits . . . achieved by the present inventive subject matter” are neither
disclosed nor suggested by the applied references (Appeal Br. 44-47; Reply
Br. 8-9).
Appellants’ arguments do not persuade us that the Examiner erred in
concluding that one of ordinary skill in the art would have been led to the
claimed subject matter within the meaning of 35 U.S.C. § 103. As set forth
by the Examiner, the device of Fan ’89 is modified to include LEDs in the
subsets in parallel as taught by both Ishizaka and Nishizawa for the benefit
of redundancy and to include a rectifier, as taught by Nishizawa, to allow
use of AC power as the power source by converting it to DC power effective
to power each parallel LED circuit over the entire AC power cycle.10
10 While not relied on by the Examiner in this rejection, Fan ’89 also teaches
LEDs—without the protested antiparallel orientation—for use with DC
power (see Fig. 4), for which modification to connect the LEDs in parallel,
as they are in Ishizaka and Nishizawa, for the benefit of redundancy would
similarly have led to the claimed subject matter.
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Appellants’ arguments that the Examiner “did not explain how it
deems that a person of ordinary skill in the art would modify the devices
disclosed in Fan [’89]” in light of the disclosures of Ishizaka and Nishizawa
(Appeal Br. 40-41) fail to address the combination as set forth by the
Examiner in which the arrangement of LEDs within a subset in Fan ’89 is
modified to be in parallel as taught by Ishizaka and Nishizawa (Final Act. 4,
7). Similarly, Appellants’ argument as to the Examiner’s reliance on
Nishizawa for a rectifier allowing parallel LEDs to function fails to identify
reversible error in the Examiner’s determination the rejected claims were
obvious over the cited art within the meaning of 35 U.S.C. § 103.
Appellants’ arguments that the modification of Fan ’89 to include
LEDs in parallel orientation, rather than in reverse parallel orientation,
would render it incapable of performing its function are unpersuasive,
particularly as to the combination including use of a rectifier, as discussed
above.
Appellants’ contentions of various “benefits . . . achieved by the
present inventive subject matter” neither disclosed nor suggested by the
applied references (Appeal Br. 44-47; Reply Br. 8—9) have no persuasive
merit. First, these contended benefits are not express limitations of the
claims, nor have Appellants demonstrated that they are inherent limitations
that arise inevitably from the express limitations recited in the claims. See
In re Self, 671 F.2d 1344, 1348 (CCPA 1982) (“Appellant’s arguments fail
from the outset because . . . they are not based on limitations appearing in
the claims.”). Second, the contention that these benefits are neither
suggested nor disclosed by the cited prior art wholly fails to rebut the prima
facie case of obviousness because, to do so, Appellants must show, by the
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preponderance of the evidence of record, that the claimed invention imparts
unexpected results and that the unexpected results are reasonably
commensurate with the scope of protection sought by the claim on appeal.
In re Grasselli, 713 F.2d 731, 743 (Fed. Cir. 1983); In re Klosak, 455 F.2d
1077, 1080 (CCPA 1972). Contentions such as those in the Appeal and
Reply Briefs are not sufficient to bear Appellants’ burden. In re Pearson,
494 F.2d 1399, 1405 (CCPA 1974) (“Attorney’s argument. . . cannot take
the place of evidence.”).
Claims 1, 3, 6—10, 12—16, 30, 125—128, and 131
While separately set forth, the Examiner relies on Fan ’89, Ishizaka,
and Nishizawa in substantially the same manner as in rejecting independent
claims 27 and 42, discussed above. Compare Final Act. 9-11, with id. at 3—
7; see also Ans. 5.
Appellants similarly rely on the same arguments, proffered separately
for independent claim 1, independent claim 12, and independent claims 30
and 125 (compare Appeal Brief 47—53, with Appeal Br. 36-47; see also
Reply Br. 3—9), which are unpersuasive of harmful error for the reasons
discussed above.
Fan ’89 in view of Lee ’71 or Lin — Claims 4 and 5
In rejecting claims 4 and 5, the Examiner relies on Fan ’89 in the main
and further relies on Lee ’71 or Lin for the mirrored layer disposed between
the submount substrate and the insulator layer in the interconnection
submount. Final Act. 15—16.
Because the rejection of independent claim 1, from which claims 4
and 5 ultimately depend, as anticipated by Fan ’89 is not well founded, and
neither Lee ’071 nor Lin cures the deficiencies of Fan ’89, we reverse the
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rejection of claims 4 and 5, but enter the following new ground in
accordance with our authority under 35 C.F.R. § 41.50(b).
Claims 4 and 5 are unpatentable over Fan ’89 in view of Ishizaka and
Nishizawa (as discussed above), in further view of Lin. As relied on by the
Examiner in the obviousness rejection of claim 1, Fan ’89 teaches a plurality
of LEDs mechanically connected by a common substrate on which the LEDs
are formed (LED dies) and an interconnection submount, which electrically
interconnects the LED dies. Fan ’89 25—26, Figs. 7, 9. Fan’89 teaches
that the LED dies (subunits) can be connected in series. Fig. 9. Fan ’89 also
discloses LEDs in an array on a die arranged in series (Fig. 4), for use with
DC power, and with two series arranged in reverse parallel orientation to
each other (Fig. 5), for use with unrectified AC power.
Uses of light emitting devices arranged in subunits comprising more
than three parallel circuits, wherein the subunits are then joined together in
series is taught by each of Ishizaka and Nishizawa. Ishizaka, Fig. 3;
Nishizawa, Fig. 5 A. The benefit of arranging LEDs in parallel circuits to
allow for redundancy that provides for function even if an LED is defective
or fails is manifest. Nishizawa also teaches the use of a rectifier (REC) to
convert AC power to DC. Nishizawa col. 14,1. 65—col. 15,1. 3, Fig. 5A.
One of ordinary skill in the art would have found it obvious at the
time of the invention to have modified the light emitter of Fan ’89, as
depicted in Figure 9, to include more than three parallel circuits of LEDs on
each of the LED dies to obtain the benefit of redundancy taught by Ishizaka
and Nishizawa. Omitting the antiparallel circuits of LEDs, required for AC
power use in the absence of an included rectifier, would have been obvious
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for use with provided DC power, or with rectified AC power, as they would
not be required.
As to the added limitations of claim 3, Fan ’89 discloses an
interconnection submount comprising a submount substrate (submount
assembly 304), an insulator layer on the submount (insulating layer 306),
and a pattern of electrically conductive elements on the insulator layer and
configured to interconnect respective contacts of the light emitting devices
into the array of light emitting devices (control and driving circuit 308). Fan
’89 125, Fig. 7.
Claim 4, depending from claim 3, further recites “wherein the
interconnection submount further comprises a mirrored layer disposed
between the submount substrate and the insulator layer.”
As set forth above, Fan ’89 lacks a mirrored layer between the
submount substrate and the insulator layer.
Lin was identified as 35 U.S.C. § 102(e) prior art on the basis that
there is not sufficient written description support for the claimed invention in
the one provisional application (no. 60/885,937, filed January 22, 2007 (“the
’937 provisional”)), of three relied on, for the claimed structure of an
“interconnection submount. . . comprising] a mirrored layer disposed
between the submount substrate and the insulator layer” required by claim 4.
Final Act. 16. Appellants did not contest Lin’s status as 35 U.S.C. § 102(e)
prior art. See generally Appeal Br.
On this record, we likewise do not find sufficient written support prior
to the effective date of Lin. See In re Giacomini, 612 F.3d 1380, 1383 (Fed.
Cir. 2010) (“An important limitation is that the provisional application must
provide written description support for the claimed invention.”). In the ’937
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provisional, the disclosure as to the use of a mirror layer is limited to the use
of particular “new chip platforms . . . [that] are moving to a substrateless
chip/dice assembly” and “[i]n these cases, the ‘thin LED’ structures are
mounted to a supporting substrate with a mirror layer to direct light out [of]
the device (GaN) side.” ’937 provisional, 3,11. 1—5. This disclosure does
not, however, support “a mirrored layer disposed between the submount
substrate and the insulator layer,” as required by claim 4. While the ’937
provisional also discloses use of an “insulating ‘buffer layer,”’ it only does
so for an express alternative to the particular “new chip platforms” for which
use of a mirror layer is disclosed. ’937 provisional, 2,1. 23—3,1. 5. The ’937
provisional thus lacks sufficient written description of an “interconnection
submount. . . comprising] a mirrored layer disposed between the submount
substrate and the insulator layer” required by claim 4 (emphasis added).
Turning to Lin as prior art, Lin discloses an LED package structure
comprising, in order, a silicon substrate, a reflective layer disposed on the
silicon substrate, a transparent insulating layer disposed on the reflective
layer, a conductive layer disposed on the transparent insulating layer, and a
plurality of LEDs disposed on the conductive layer. Lin, Abstract. Lin
further teaches that use of the reflective layer in such a structure improves
light utility. Lin H 6—8.
One of ordinary skill in the art at the time of the invention would have
found it obvious to have included a reflective layer between the submount
substrate and the insulator layer as taught by Lin for the benefit of improved
light utility.
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Claim 5, depending from claim 4, further recites “wherein all of the
electrical interconnections of light emitting devices are provided by the
pattern of electrically conductive elements.”
The further limitation of claim 5 is met by the control and driving
circuit 308 of Fan ’89, discussed above, as it “controls] the LED array . . .
through interconnections 310.” Fan ’89 125, Fig. 7.
Claims 4 and 5 are, accordingly, unpatentable for obviousness over
Fan ’89 in view of Ishizaka and Nishizawa (as discussed above), in further
view of Lin.
Fan ’89 in view of Lee ’16 —Claim 45
In rejecting claim 45, the Examiner relies on Fan ’89 in the main and
further relies on Lee ’ 16 for the rectifying bridge to convert an AC source
into a DC source.
Because the rejection of independent claim 42, from which claim 45
ultimately depends, over Fan ’89 alone is not well founded, we reverse the
rejection of claim 45, but enter the following new ground in accordance with
our authority under 35 C.F.R. § 41.50(b).
Claim 45 is unpatentable over Fan ’89 in view of Ishizaka and
Nishizawa (as discussed above), in further view of Lee ’16. Fan ’89 teaches
fabrication of an LED array in which a deep trench is etched down to a
substrate 104 between adjacently formed LEDs, comprising monolithic n-
type layer 112 and monolithic p-type layer 116, to electrically isolate the
discrete LEDs from one another. Fan ’89 119, Fig. 3. A first monolithic n-
type layer 112 and first monolithic p-type layer 116 bound a light emitting
layer 114 in the formed LEDs. Id. The formed LEDs in the LED array are
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then connected to elements of metal layer 124 that interconnect the LEDs
via n-contacts 118 and p-contacts 120. Id.
As to the recited connectivity, the implicated structure connects the
first, second, and third light emitting devices in parallel, the fourth, fifth, and
sixth light emitting devices in parallel, and the two groups of light emitting
devices in series. Appeal Br. (Claims App.) A-2. This structure is met by
the combination of Fan ’89 in view of Ishizaka and Nishizawa as discussed
above.
Claim 45, depending from claim 43, which depends from claim 42,
further requires that the “light emitter further comprises a rectifying bridge.”
Lee ’16 discloses a bridge rectifier 350 in a circuit having at least
three series of LEDs in parallel and is provided with an AC power source
1000. Lee ’16 H 152, 168—169, Fig. 16. As discussed above with respect to
Nishizawa, the provision of a rectifier allows for use of an AC power supply,
and one of ordinary skill in the art would have found it obvious at the time
of the invention to have modified the light emitter by addition of a bridge
rectifier to allow use of an AC power supply with reduced flicker.
Claim 45 is, accordingly, unpatentable for obviousness over Fan ’89
in view of Ishizaka and Nishizawa (as discussed above), in further view of
Lee ’16.
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CONCLUSION
The Examiner’s indefiniteness rejection of claims 8 and 9 is reversed.
The Examiner anticipation rejection of claims 27, 28, 42, 43, 48, 49,
and 130 over Fan ’89 is reversed.
The Examiner’s obviousness rejections of claims 1, 3, 6—10, 12—16,
27, 28, 30, 42, 43, 48, 49, 125—128, 130, and 131 over Fan ’89 in view of
Ishizaka and Nishizawa are affirmed.
The Examiner’s obviousness rejection of claims 4 and 5 in view of
Fan ’89 in view of Lee ’71 or Lin is reversed.
The Examiner’s obviousness rejection of claim 45 in view of Fan ’89
in view of Lee ’ 16 is reversed.
Pursuant to 37 C.F.R. § 41.50(b), we enter a NEW GROUND OF
REJECTION under 35 U.S.C. § 103(a) both for claims 4 and 5 over Fan ’89
in view of Ishizaka, Nishizawa, and Lin and for claim 45 over Fan ’89 in
view of Ishizaka, Nishizawa, and Lee ’16.
37 C.F.R. § 41.50(b) provides “[a] new ground of rejection pursuant
to this paragraph shall not be considered final for judicial review.” Section
41.50(b) also provides:
When the Board enters such a non-final decision, the appellant,
within two months from the date of the decision, must exercise
one of the following two options with respect to the new ground
of rejection to avoid termination of the appeal as to the rejected
claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new Evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the prosecution
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Appeal 2016-002222
Application 12/017,600
will be remanded to the examiner. The new ground of rejection
is binding upon the examiner unless an amendment or new
Evidence not previously of Record is made which, in the
opinion of the examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner reject the
claims, appellant may again appeal to the Board pursuant to this
subpart.
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same Record. The
request for rehearing must address any new ground of rejection
and state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.
Further guidance on responding to a new ground of rejection can be
found in the Manual of Patent Examining Procedure § 1214.01.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-fN-PART; NEW GROUND OF REJECTION
PURSUANT TO 37 C.F.R, $ 41.50(b)
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