Ex Parte Nazarian et al

Patent Trial and Appeal Board

Feb 28, 2014

11928865 (P.T.A.B. Feb. 28, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/928,865 10/30/2007 Hagop Nazarian 3186.5190000 7931
105945 7590 02/28/2014
Sterne, Kessler, Goldstein & Fox P.L.L.C.
1100 New York Avenue, NW
Washington, DC 20005
EXAMINER
THAI, TUAN V
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
02/28/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HAGOP NAZARIAN and ALI POURKERAMATI
____________

Appeal 2011-009700
Application 11/928,865
Technology Center 2100
____________

Before JEAN R. HOMERE, JEFFREY S. SMITH, and
DANIEL N. FISHMAN, Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2011-009700
Application 11/928,865

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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 3, 4, 7-9, 12-14, 20, and 22, which are the only claims
remaining in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Illustrative Claim
1. A memory device, comprising:
an array of memory cells; and
a partitioning system configured to address a first portion of the array
in a single level cell mode, and a second portion of the array in a multi-level
cell mode,
wherein the partitioning system is configured to distinguish between
the first and second array portions based on first and second programmable
address pointers provided thereto, and
wherein the partitioning system identifies all the memory cells in the
array having addresses between the first and second programmable address
pointers as the first portion, and all remaining memory cells in the array as
the second portion.

Prior Art
Rolandi EP 0788113 A1 Aug. 6, 1997
Lee US 5,930,167 Jul. 27, 1999
Nakano US 2007/0211530 A1 Sept. 13, 2007

Examiner’s Rejections
Claims 1, 3, 4, 7-9, and 12-14 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Rolandi (hereinafter referred to as “Thomson”)
and Nakano.
Claims 20 and 22 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Lee and Nakano.
Appeal 2011-009700
Application 11/928,865

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ANALYSIS
Section 103 rejection of claims 1, 3, 4, 7-9, and 12-14
Claim 1 recites “the partitioning system identifies all the memory cells
in the array having addresses between the first and second programmable
address pointers as the first portion, and all remaining memory cells in the
array as the second portion.” The Examiner finds Nakano teaches a memory
having single level and multi-level portions, and a table identifying which
memory addresses are in the single level portion, and which addresses are in
the multi-level portion. Ans. 5. The Examiner further finds the table entry
for the start of a portion, and the table entry for the end of the portion, teach
“the first and second programmable address pointers” within the meaning of
claim 1. Id. Appellants contend storing all addresses identifying a portion
of memory as single or multi-level is different than identifying memory
addresses between first and second programmable address pointers. App.
Br. 5,. Appellants further contend modifying the table of Nakano to contain
a start address and an end address of a portion, rather than the address for
each cell in the portion, is impermissible hindsight. Reply Br. 2.
We agree with the Examiner that the table of Nakano includes a first
entry, or “pointer,” to the first address of a portion, and a second pointer to
the last address of the portion. All addresses in the table of Nakano between
the first and second “pointers” are identified by the system as within the
portion. Appellants have not provided a definition of “the partitioning
system identifies all the memory cells in the array having addresses between
the first and second programmable address pointers as the first portion” that
excludes the table for identifying all memory cells having addresses between
first and last table entries as a first portion as taught by Nakano. Further,
Appeal 2011-009700
Application 11/928,865

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Appellants have not provided persuasive evidence or argument to show that
using first and last address pointers, in place of pointers for all addresses, to
identify a portion of memory was “uniquely challenging or difficult for one
of ordinary skill in the art.” See Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR Int’l Co. v. Teleflex, Inc.,
550 U.S. 398, 419 (2007)).
We sustain the rejection of claim 1 under 35 U.S.C. § 103. Appellants
do not present arguments for separate patentability of claims 3, 4, 7-9, and
12-14, which fall with claim 1.

Section 103 rejection of claims 20 and 22
Appellants contend the combination of Lee and Nakano does not
teach transferring data from a first location in the memory having a multi-
level cell format to a second location in the memory having a single level
cell format as required by claim 20. App. Br. 7. In particular, Appellants
contend Nakano “teaches away” from transferring data from multi-level to
single level memory, because Nakano teaches writing data to multi-level
memory when no available space is left in single level memory. App. Br. 8.
According to Appellants, going from multi-level to single level is not
intuitive, because more memory space is needed. Reply Br. 3.
“A reference may be said to teach away when a person of ordinary
skill, upon [examining] the reference, would be discouraged from following
the path set out in the reference, or would be led in a direction divergent
from the path that was taken by the applicant.” Para-Ordnance Mfg., Inc. v.
SGS Importers Int’l, Inc. 73 F.3d 1085, 1090 (Fed. Cir. 1995) (quoting In re
Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994)). Appellants have not identified
Appeal 2011-009700
Application 11/928,865

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any teaching of Nakano that discourages an artisan to avoid transferring
data from multi-level to single level memory. We agree with the Examiner
(Ans. 28) that the combination of Lee and Nakano teaches using multi-level
memory for archival storage, and using single level memory for faster
performance.
We sustain the rejection of claim 20 under 35 U.S.C. § 103.
Appellants do not present arguments for the patentability of claim 22 which
falls with claim 20.

DECISION
The rejection of claims 1, 3, 4, 7-9, and 12-14 under 35 U.S.C.
§ 103(a) as being unpatentable over Thomson and Nakano is affirmed.
The rejection of claims 20 and 22 under 35 U.S.C. § 103(a) as being
unpatentable over Lee and Nakano is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

AFFIRMED

sld