Ex Parte Nair et al

Board of Patent Appeals and Interferences

May 25, 2010

10244434 (B.P.A.I. May. 25, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte RAVI NAIR, JOHN KEVIN O’BRIEN,
KATHRYN MARY O’BRIEN, PETER HOWLAND ODEN,
and DANIEL ARTHUR PRENER
____________

Appeal 2008-004375
Application 10/244,434
Technology Center 2100
____________

Decided: May 25, 2010
____________

Before JOHN C. MARTIN, MAHSHID D. SAADAT,
and CARLA M. KRIVAK, Administrative Patent Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL
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This is a decision on appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1-53, which are all of the claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention relates to a method of emulating the memory
sharing behavior of a multiprocessing computer system on another
multiprocessing computing system having a different memory sharing
behavior when the host multiprocessing system supports a weak or relaxed
consistency model, while the target system specifies a strong or stringent
consistency model (Spec. 8:15-21). An understanding of the invention can
be derived from a reading of independent claims 1, 24, and 49, which are
reproduced as follows:
1. A method of emulation in a multiprocessor system,
comprising:
performing an emulation in which a host multiprocessing
system of said multiprocessor system supports a weak consistency
model, and the target multiprocessing system of the multiprocessor
system supports a strong consistency model.

24. A method of ensuring memory consistency in a
multiprocessing system, comprising:
determining whether an instruction is a load or a store;
if it is determined that the instruction is a load or a store, then
resolving an address of said instruction and determining whether the
address is stored in a local look-aside buffer (LLB);
if the address is in the LLB, then determining whether the
location is in a shared-read state; and
if it is determined that the location is in a shared-read state, then
determining whether the current address is a write,
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wherein if the current address is not a write, then performing an
emulation of the instruction.

49. A storage reference table (SRT) for a shared
multiprocessor system, comprising:
a table containing as many entries as a number of store
references, and wherein each entry contains a plurality of fields
including an address field and an old-value field for storing original
values for recovery,
wherein said table stores information concerning a shared write
status of said entries.

The Examiner relies on the following prior art references:
James US 5,574,922 Nov. 12, 1996
Ebrahim US 5,905,998 May 18, 1999
Egolf US 6,763,328 B1 Jul. 13, 2004
(filed Jun. 15, 2000)
Agesen US 6,961,806 B1 Nov. 1, 2005
(filed Dec. 10, 2001)

Claims 1, 52, and 53 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Agesen.
Claims 24-27 and 39-48 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by James.
Claims 49-51 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Ebrahim.
Claims 2-9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Agesen and James.
Claims 10-18 and 23 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ebrahim and Egolf.
Claims 19-22 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ebrahim and Egolf in view of James.
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Claims 28-38 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over James and Ebrahim.1
We make reference to the Briefs (Appeal Brief, filed on May 14,
2007, and Reply Brief, filed on December 31, 2007) and the Answer (filed
October 31, 2007) for their respective details. Only those arguments
actually made by Appellants have been considered in this decision.
Arguments which Appellants could have made but did not make in the
Briefs have not been considered and are deemed to be waived. See
37 C.F.R. § 41.37(c)(1)(vii).

ISSUES
1. Under 35 U.S.C. § 102(e), does Agesen have a disclosure
which anticipates the invention set forth in claims 1, 52, and 53?
2. Under 35 U.S.C. § 102(b), does James have a disclosure which
anticipates the invention set forth in claims 24-27 and 39-48?
3. Under 35 U.S.C. § 102(b), does Ebrahim have a disclosure
which anticipates the invention set forth in claims 49-51?
4. Under 35 U.S.C. § 103(a), with respect to the remaining
appealed claims, would one of ordinary skill in the art at the time of the
invention have found the claimed invention obvious over various
combinations of Agesen, James, Ebrahim, and Egolf?

1 The details of these rejections are repeated on pages 3-28 of the Answer.
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PRINCIPLES OF LAW
Anticipation
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375-76 (Fed. Cir. 2005) (citing Minn. Mining &
Mfg. Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565
(Fed. Cir. 1992)). “Anticipation of a patent claim requires a finding that the
claim at issue ‘reads on’ a prior art reference.” Atlas Powder Co. v. IRECO,
Inc., 190 F.3d 1342, 1346 (Fed. Cir. 1999).
Obviousness
The test for obviousness is what the combined teachings of the
references would have suggested to one of ordinary skill in the art. See In re
Kahn, 441 F.3d 977, 987-88 (Fed. Cir. 2006); In re Young, 927 F.2d 588,
591 (Fed. Cir. 1991); In re Keller, 642 F.2d 413, 425 (CCPA 1981).
The Examiner can satisfy this burden by showing “‘some articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness.’” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007)
(quoting Kahn, 441 F.3d at 988).

ANALYSIS
35 U.S.C. § 102(e) rejection of claims 1, 52, and 53 over
Agesen
The Examiner indicates (Ans. 3-7) how the various limitations of
these claims are read on the disclosure of Agesen with respect to the virtual
machines supporting weak consistency and strong consistency. Appellants’
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arguments in response assert that the disclosed implementation of virtual
machines does not meet the claimed “host multiprocessing system”
emulating a “target multiprocessing system” (App. Br. 9). Appellants
further argue that the cited portion at column 15 of Agesen does not describe
a virtual machine having a strong consistency (App. Br. 9-10). Finally,
Appellants point out that Agesen does not use the term “consistency model”
in the same context described by one of the inventors of the instant
application in a published book2 and cannot anticipate the claimed subject
matter (App. Br. 10-11).
Upon a review of the disclosure of Agesen, however, we find
sufficient evidence to support the Examiner’s position. As disclosed at
column 2, lines 48-58, of Agesen, a virtual machine is a software abstraction
or “virtualization” of an actual physical computer system wherein the virtual
devices “emulate the corresponding components of an actual computer.”
Therefore, the virtual machines “emulate” the actual computer or the target
multiprocessing system. Additionally, we disagree with Appellants’
argument (App. Br. 9) that the virtual machines of Agesen do not meet the
claimed host multiprocessor used to emulate a target multiprocessor system.
In that regard, as argued by the Examiner (Ans. 30), the claims merely
require performing an emulation, but do not recite that the host
multiprocessing system emulates a target multiprocessing system.
We also agree with the Examiner’s findings (Ans. 7 and 30) that
Agesen further discloses supporting weak consistency and strong
consistency models in different situations. In particular, Agesen discloses at

2 Appellants refer to the Nair declaration filed under 37 C.F.R. § 1.132 and
included in the EVIDENCE APPENDIX of the Appeal Brief.
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column 15, lines 53-63, that choosing between different trace semantics
depends on the consistency guarantee required in each situation, such as
post-write and bracketing, where different consistency models are supported.
Agesen further describes at column 15, lines 58-61, using strong consistency
for bracketing, while a weak consistency is followed for post-write at
column 15, lines 63-67. We also agree with the Examiner (Ans. 30) that
these two situations may apply to two different virtual machines wherein
different trace semantics are used. See col. 14, ll. 58-65. In other words,
Agesen does not require that each of the trace semantics having weak or
strong consistency must be applied to every virtual machine in the
multiprocessing system. Therefore, contrary to Appellants’ argument (App.
Br. 9-10), different virtual machines having weak consistency or strong
consistency in Agesen meet the broad claimed recitation of a host
multiprocessing system supporting a weak consistency model and a target
multiprocessing system supporting a strong consistency model.
Finally, we remain unpersuaded by Appellants’ arguments (App. Br.
10-11) with respect to the concepts of memory coherence and memory
consistency and how Agesen uses the term “consistency” in the sense of
memory coherence. Appellants rely on a book by a co-inventor for the
definitions of these terms and state that the terms strong and weak
consistency in the present application are different from the context in which
Agesen discloses strong and weak consistency (id.).
As argued by the Examiner (Ans. 31-32), Appellants define strong
and weak consistency by relying on two technical articles discussed on
pages 6-8 of the Specification, excerpts of which are quoted by the Examiner
on page 32 of the Answer. As stated by the Examiner (id.), neither of these
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documents defines the term “memory consistency” beyond its plain
meaning. The Examiner also finds that the book referred to by Appellants
and mentioned in the § 132 declaration for distinguishing between memory
consistency and memory coherence cannot be relied on because it has a
publication year of 2005, which is after the application filing date of 2002
(Ans. 33).3 We agree with the Examiner’s findings and conclusion based on
the evidence presented by Appellants in their § 132 declaration and further
find that Appellants do not challenge either of these findings in their Reply
Brief.
In view of the above discussion, since all of the claimed limitations
are present in the disclosure of Agesen, the Examiner’s 35 U.S.C. § 102(e)
rejection of independent claims 1, 52, and 53, which are argued together as
one group, is sustained.

35 U.S.C. § 102(b) rejection of claims 24-27 and 39-48 over
James
Claims 24-27
With respect to claim 24, Appellants contend that the disclosure of
James does not meet the sequence of steps recited in claim 24, which reflects
the sequence shown in the flowchart of Appellants’ Figure 8 (App. Br. 12).
Appellants argue that the relied on portions of James at column 7, lines 44-
55, do not describe determining whether an instruction is a load or a store

3 The Examiner provides copies of the book’s sale information on
http://www.amazon.com website, which shows various information
regarding the book Appellants relied on including the publishing date of the
book shown as June 3, 2005.
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while the portion at column 7, lines 24-30, also fails to disclose resolving an
address contingent upon that determination (id.).
We agree with the Examiner (Ans. 33) that the flow chart of
Appellants’ Figure 8 cannot be used for determining the scope of the recited
method of claim 24. Furthermore, as argued by the Examiner (id.), while
James does not explicitly disclose the step of determining whether an
instruction is a load or store, any of the instruction sequences SameLoad8 or
SameStore8 are performed based on the specific situation, as discussed at
column 7, lines 44-53. In other words, when the controller disclosed at
column 6, lines 49-64, calls the specific instruction sequence, a
determination is also made as to which instruction sequence is being
executed. Additionally, as the Examiner finds (Ans. 34), James discloses at
column 7, lines 24-30, that in either case the address is resolved by
translating the virtual address into the corresponding physical address by
looking up the address in the processor local table called a translation look-
aside buffer.
Appellants further argue that James does not describe determining
whether the address is stored in a local look-aside buffer (LLB) because the
portion of James at column 7, lines 24-30, presumes the address is in the
translation look-aside buffer (TLB) (App. Br. 12). We again agree with the
Examiner (Ans. 34) that another situation described at column 7, lines 31-
37, of James describes a process in which a trap is generated to suspend
normal program execution when the address is not in the TLB. As such,
James meets the claimed requirement by determining whether the address is
in the TLB and updating the address if it is not found in the TLB.
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Regarding the remaining argument made by Appellants (App. Br. 13)
that the look-aside buffer of James has no shared-read bits, we find the
Examiner’s analysis (Ans. 10) of James at column 8, lines 15-24, to be
reasonable and adopt those findings as our own. We particularly agree with
the Examiner (Ans. 34-35) that James’s instructions apply to data in memory
shared by different processors and SameLoad8 refers to a shared-read state.
We also agree with the Examiner’s finding with respect to the disclosure at
column 8, lines 15-24, that making a determination if address1 is written to
meets the claimed step of determining if the location is in a shared-read state
and whether the address is a write. Similarly, we agree with the Examiner
(Ans. 10) that James performs emulation by executing instructions in virtual
memory when the actual physical memory is smaller in size than the
processor address space by translating the virtual memory into a
corresponding address in the physical memory. See col. 7, ll. 11-30.
We further agree with the Examiner (Ans. 35-36) that the discussion
of memory consistency/coherency made by Appellants (App. Br. 13) is
unpersuasive since the process disclosed by James maintains consistency
between the cache and the shared memory regardless of the details of cache
coherence. See col. 7, ll. 3-10. Therefore, based on the same reasons
discussed above regarding the definitions of memory consistency and
memory coherency, we remain unpersuaded by Appellants’ contentions and
find that James is concerned with the issue of memory consistency in shared
memory. We further note that Appellants provide no additional arguments
or challenges in the Reply Brief in response to these Examiner’s findings
and merely repeat that James provides no suggestion of the flowchart in
Figure 8 of the instant application, nor of any claimed steps (Reply Br. 5-6).
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Regarding claims 25-27, Appellants argue that the cited portions at
column 20, lines 7-28, of James do not place a memory barrier into an
emulation stream, and instead, present an address to a cache and set a
trapping if the address is not valid or uncacheable (App. Br. 13). Appellants
further assert that memory barriers do not access a cache, but maintain
ordering of memory operations as seen by multiple processors (id.).
However, as argued by the Examiner (Ans. 37), the claimed memory barrier
reads on the trap James generates if the address is not valid, which inhibits
storage updates until the problem is solved. See col. 20, ll. 7-28, 32-36.
Claims 39-48
Regarding claim 39, Appellants contend that the portion of James at
column 8, lines 30-35, discloses no stub code added at the end of a
translation and fails to meet the recited claim language (App. Br. 14). The
Examiner responds by pointing to setting the result.fail to FAIL in James
and arguing that the result of such action meets the claim limitations (Ans.
37-38). We agree with the Examiner’s position and find that the claim
limitations are met because the FAIL indication is a stub code which ends
the instruction and prevents other processors from changing the values to
“shared-write” locations. See col. 8, ll. 29-40.
With respect to claims 40-48, we note that Appellants merely restate
the claim limitations and allege that James includes no disclosure that meets
those claimed requirements (App. Br. 14-15). We find the Examiner’s
findings with respect to these claims and the response provided to
Appellants’ arguments (Ans. 37-39), which remain unchallenged by
Appellants in the Reply Brief, to be reasonable.
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Therefore, in view of our review of James and the Examiner’s
response to Appellants’ arguments discussed above, we sustain the
Examiner’s 35 U.S.C. § 102(b) rejection of claims 24-27 and 39-48 over
James.

35 U.S.C. § 102(b) rejection of claims 49-51 over Ebrahim
Claim 49
With respect to claim 49, Appellants contend (App. Br. 16) that the
Dtags of Ebrahim do not meet the claimed old-value field for storing
original values for recovery. Appellants assert (id.) that the table described
at column 10, lines 34-41, of Ebrahim is a standard cache including tags that
are associated with each cache line, and thus fails to meet the claimed
storage reference table (SRT). Appellants further argue that the description
at column 4, lines 50-55, of Ebrahim are “Shared Modified (O)” and
“Shared Clean (S)” status and not the claimed “shared write status” (id.).
The Examiner responds (Ans. 39) that the Dtags disclosed at column
26, lines 22-34, of Ebrahim are old tags that hold the original values
including the cache status and address bits. With respect to the claimed
“shared write status,” the Examiner points to the definition of “Shared
Modified (O)” at column 24, lines 58-61, of Ebrahim and states that the
shared modified (O) is the status wherein data has been modified by the data
processor and may be stored in one or more other cache memories (Ans. 39).
The Examiner further responds that Appellants’ arguments regarding the
SRT are not commensurate in scope with claim 49 since having cache
storage is not precluded by the claim language (Ans. 40).
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We find that the Dtags of Ebrahim are disclosed at column 26, lines
22-34, and contain the state for the corresponding Etag as part of multiple
writeback transactions that provide multiple writeback buffers and an equal
number of Dtags. See also col. 26, ll. 11-14. Ebrahim further discloses the
writeback of displaced cache data blocks, called “dirty victims,” which
allow the writeback transaction to be handled independent of the transaction
that stores a new data block. See col. 27, ll. 19-32.
As such, we disagree with Appellants that the Dtags do not contain an
old-value field for storing original values since a lookup on the Dtag
indicates the corresponding Etag state. In other words, using the “dirty
victim” mechanism, which handles the writeback of displaced cache data
blocks, the writeback transaction stores a new data block in the cache line
previously occupied by a dirty victim and avoids the ordering constraints
associated with such writeback transactions. See col. 27, ll. 27-32.
Therefore, Ebrahim’s Dtag includes an old-value field for storing the
original or the previous value for recovery when the writeback transaction of
displaced cache data blocks is performed.
Claim 50
Regarding claim 50, Appellants contend (App. Br. 17) that the relied
on portion of Ebrahim at column 2, lines 56-61, does not discuss a memory
order buffer (MOB). Appellants further argue that the difference between
memory consistency and memory coherency defines how the recited features
of claim 50 are different from the disclosure of Ebrahim (id.). We agree
with the Examiner’s response (Ans. 40) that the system controller of
Ebrahim maintains the order of memory references because data blocks are
stored wherein access to a data block that maps to the same cache line as a
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pending, previously activated transaction is blocked until the pending
transactions are complete. See col. 2, l. 64 – col. 3, l. 2. Additionally, for
the same reasons discussed previously regarding claim 1 and argued by the
Examiner (Ans. 41-43), we disagree with Appellants’ asserted difference
between memory coherency and memory consistency as the basis for
Appellants’ contention that the disclosure of Ebrahim is not in the context of
memory consistency.
Claim 51
With respect to claim 51, Appellants argue that the Cache Index Mask
(CIM) field 194 of Ebrahim masks out some bits in the address, but does not
include the claimed mask fields indicating whether the page is accessed in a
read mode (App. Br. 18). The Examiner responds (Ans. 43) by pointing to
the relationship between the CIM fields 194 and the active transaction status
table 200 shown in Figure 13 of Ebrahim and states that the status table
includes fields 294 derived from Dtag tables 340 which indicate the status of
the transaction or whether the transaction is a write or read. We agree with
the Examiner and find that Ebrahim includes read or store status in a Dtag,
as disclosed at column 26, lines 32-49, which are added to the active
transaction status table 200 of Figure 13 as status fields 294 and provided to
CIM 194. See Figs. 5, 13; col. 51, ll. 17-22.
Therefore, based on our review of Ebrahim and the discussion made
above, we find that all of the claimed limitations are present in the disclosure
of Ebrahim and sustain the Examiner’s 35 U.S.C. § 102(b) rejection of
claims 49-51.

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35 U.S.C. § 103 rejection of claims 2-9 over Agesen and James
Appellants argue that Agesen does not relate to emulation of a target
multiprocessor on a host multiprocessor or a host multiprocessor system
supporting a weak consistency model and a target multiprocessor system
supporting a strong consistency model (App. Br. 19). Appellants further
assert that James does not overcome this deficiency of Agesen (id.).
Appellants’ remaining contentions repeat the arguments presented with
respect to claim 1 and further focus on the combination of the references
(App. Br. 19-20).
The Examiner responds by pointing to the discussion of Agesen
previously provided for claim 1 and states that both references are directed
to virtualization in which a virtual machine emulates the component of an
actual computer (Ans. 44). The Examiner further argues that even if James
is not directed to emulation, the reference relates to memory consistency in a
multiprocessor system and is reasonably pertinent to the problem of
emulation (id.). The Examiner further provides (Ans. 44-47) a detailed
explanation of why the combination of Agesen and James would have been
obvious to one of ordinary skill in the art, to which Appellants provide no
response in the Reply Brief.
We agree with the Examiner since, as discussed above with respect to
claim 1, the claims do not specifically require emulation of a target
multiprocessor on a host multiprocessor. We also find the Examiner’s
position that one of ordinary skill in the art would have found it obvious to
combine Agesen and James to be reasonable and supported by evidence of
record. Therefore, based on our review of Agesen and James and the
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discussion made above, we sustain the Examiner’s 35 U.S.C. § 103(a)
rejection of claims 2-9.

35 U.S.C. § 103 rejection of claims 10-18 and 23 over Ebrahim
and Egolf
In rejecting claim 10, the Examiner relies on column 2, lines 24-26
and 52-56, of Ebrahim for disclosing an emulator in a multiprocessing
computer system wherein a memory barrier or block prior to a memory
transaction ensures each memory transaction is blocked until predetermined
criteria are met (Ans. 21). The Examiner further asserts that Ebrahim at
column 68, lines 50-58, discloses a host computing system supporting a
weak consistency model, while a target multiprocessor system supporting a
strong consistency model is disclosed at column 61, lines 31-40 (Ans. 21).
The Examiner further relies on column 8, lines 43-46, of Egolf for teaching
emulation of a multiprocessor target computer system on a host computer
system and further relies on column 12, lines 1-9, of Egolf for teaching that
the target system supports a strong consistency model (Ans. 22).
Appellants assert that Ebrahim does not refer to an emulator in a
multiprocessor system to emulate another multiprocessor system (App. Br.
21). Appellants further contrast the processor of Ebrahim as a sequentially
consistent host with the claimed processor that Appellants characterize as a
weakly consistent host, and argue that the combination is improper because
the Dekker algorithm of Ebrahim may not work on other host processors
(id.). With respect to Egolf, Appellants assert that the reference does not
mention a multiprocessor host system and its teachings cannot be extended
to a multiprocessor host system (App. Br. 21-22). Finally, Appellants repeat
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their discussion of memory consistency and memory coherency and argue
that Egolf never talks about consistency (App. Br. 22).
Upon our review of Ebrahim and Egolf, we again agree with the
Examiner (Ans. 47) that the disclosure of Ebrahim at column 2, lines 24-26
and 52-56, relates to emulation of a multiprocessor system, where any of the
multiple sub-systems may access the main memory, as well as blocking each
memory transaction request until a set of predefined activation criteria are
met. We also agree with the Examiner’s finding (Ans. 47) that Egolf, at
column 8, lines 43-46, discloses emulation of a multiprocessor target
computer system on a host computer system wherein the host memory
addresses are mapped and used as target virtual memory addresses.
Therefore, contrary to Appellants’ assertions (App. Br. 21), Ebrahim and
Egolf disclose the corresponding claimed features.
We further agree with the Examiner (Ans. 47) that the discussion of
the Dekker algorithm in Ebrahim relates to features that are not recited in
claim 10. Additionally, we find that, as argued by the Examiner (Ans. 48),
Egolf does disclose a multiprocessor host system as “[m]ultiple processor[]
of the Host platform” at column 12, lines 1-3. As such, we find ourselves in
agreement with the Examiner’s position (Ans. 48) that even if Egolf allows
only one thread to be active on the system, contrary to Appellants’ assertion
(App. Br. 21-22), the claim does not require that all of the host processors
implement an emulator for the target system. Finally, with respect to the
meaning of the terms memory consistency and memory coherency, we also
agree with the Examiner that Appellants have failed to define these terms
beyond their plain meaning, as previously discussed above with respect to
claim 1.
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Therefore, based on our discussion of Ebrahim and Egolf, we find that
the combination of these references would have suggested to one of ordinary
skill in the art the subject matter recited in claim 10, as well as claims 11-18
and 23, which are not argued separately from claim 10 (App. Br. 21-22).

35 U.S.C. § 103 rejection of claims 19-22 over Ebrahim, Egolf,
and James
Appellants, in addition to alleging absence of any discussion of
memory consistency in Ebrahim or Egolf, argue that Ebrahim fails to
disclose reordering instruction operations to minimize a number of memory
barrier instructions (App. Br. 23). The Examiner refers to the previously
discussed memory consistency and memory coherency and responds (Ans.
50) that reordering instruction operations is not recited in any of claims 19-
22. The Examiner further states (id.) that while reordering appears only in
claim 13, Ebrahim nonetheless discloses at column 57, lines 52-63, that two
transactions may be active at the same time, which reorders the transactions
by executing them simultaneously instead of blocking one until the other one
is complete.
Therefore, the combination of Ebrahim, Egolf, and James would have
suggested to one of ordinary skill in the art at the time of the invention the
subject matter recited in claims 19-22.

35 U.S.C. § 103 rejection of claims 28-38 over James and
Ebrahim
Claims 28-32
Appellants assert that the cited portion at column 25, lines 29-33, of
Ebrahim includes no reference to the minimization of the number of memory
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barrier instructions in an emulation (App. Br. 24). Appellants further
contend that the Examiner discusses maintaining coherency while memory
consistency is the subject of the application (id.). In response, the Examiner
refers to the discussion of reordering instruction operations provided for
claims 19-22 above and points out (Ans. 51) that the issue concerning
memory consistency and memory coherency is also previously addressed
with respect to claim 50. For the same reasons discussed above with respect
to claims 19-22 and 50, we agree with the Examiner’s arguments.
Claims 33-38
Appellants argue that James does not produce codes and includes no
method for insertion of codes (App. Br. 24). The Examiner responds by
pointing to column 8, lines 58-61, of James for teaching a distinct results.fail
code that is returned if the first address1 value is a bad virtual address (Ans.
51). We find the Examiner’s finding to be supported by evidence of record
and find no response by Appellants in the Reply Brief.
Appellants further contend that the transaction table of Ebrahim is not
for memory reordering and in fact, Ebrahim includes a centralized controller
that collects all memory references in whatever order they arrive (App. Br.
24). However, we again agree with the Examiner (Ans. 51-52) that Ebrahim
teaches insertion of codes by adding a corresponding entry into the MOB
table. See col. 2, ll. 56-64. Additionally, we agree with the Examiner (Ans.
52) that while a memory order buffer for the purpose of “memory ordering
between operations to various addresses in memory by a single emulated
target processor” and an “appearance of completing memory operations in
the order” may not be disclosed in the references, these features are not
recited in the claims.
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Finally, Appellants repeat their discussion related to “emulating
multiprocessor memory consistency” and conclude that the references
cannot be combined because they do not emulate anything (App. Br. 25).
As asserted by the Examiner (Ans. 52), the references are related to
multiprocessor memory consistency, which is the only recited function in the
preamble of claim 33 (“[a] method of inserting code for maintaining
consistency within a group of instructions in a multiprocessor system”). As
such, we also agree with the Examiner that, while emulation was previously
discussed with respect to claims 24 and 49 above, emulation is not recited in
claims 33-38.
Therefore, based on our analysis of the applied prior art and the
discussions made above, we find that the combination of James and Ebrahim
would have suggested to one of ordinary skill in the art the subject matter
recited in claims 28-38.

CONCLUSION
On the record before us, we find no error in the Examiner’s 35 U.S.C.
§ 102 rejections of claims 1, 52, and 53 over Agesen, of claims 24-27 and
39-48 over James, and of claims 49-51 over Ebrahim. We also find no error
in the Examiner’s 35 U.S.C. § 103(a) rejections of the remaining claims as
obvious over various combinations of Agesen, James, Ebrahim, and Egolf.

ORDER
The decision of the Examiner rejecting claims 1-53 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
Appeal 2008-004375
Application 10/244,434

21

AFFIRMED

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