Ex Parte Mutlu et al

Patent Trial and Appeal Board

Aug 24, 2016

11835435 (P.T.A.B. Aug. 24, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111835,435 08/08/2007
69316 7590 08/26/2016
MICROSOFT CORPORATION
ONE MICROSOFT WAY
REDMOND, WA 98052
FIRST NAMED INVENTOR
OnurMutlu
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
320600.01 1438
EXAMINER
PATEL, HIRENP
ART UNIT PAPER NUMBER
2196
NOTIFICATION DATE DELIVERY MODE
08/26/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
usdocket@microsoft.com
chriochs@microsoft.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ONUR MUTLU and THOMAS MOSCIBRODA
Appeal2014-008214
Application 11/835,435
Technology Center 2100
Before JEFFREY A. STEPHENS, NORMAN H. BEAMER, and
SCOTT B. HOWARD, Administrative Patent Judges.
STEPHENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants 1 seek our review under 35 U.S.C. § 134(a) from the
Examiner's Final Office Action ("Final Act.") rejecting claims 1, 3-5, 9, 10,
and 12-20, which are all the claims pending in the application. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm in part.
1 The real party in interest is identified as Microsoft Corporation. (App. Br.
1.)
Appeal2014-008214
Application 11/835,435
Claimed Subject Matter
The claimed invention generally relates to memory request scheduling
in shared memory controllers. (Title; Abstract.) Claims 1 and 12,
reproduced below with disputed limitations emphasized, are illustrative:
1. A computer-implemented memory management system,
compnsmg:
a request buffer for receiving memory access requests to a
shared memory from multiple threads; and
a scheduling component for prioritizing scheduling of
requests of a given thread of said multiple threads to increase
parallel execution of the given thread requests, such that
whenever a request of the given thread is in-progress, one or
more remaining requests of the given thread are scheduled
before scheduling requests of other threads of said multiple
threads that are not in-progress, wherein a thread of said
multiple threads is in-progress whenever a memory access
request from that thread to the shared memory is currently being
serviced.
12. A computer-implemented method of managing memory,
compnsmg:
receiving memory access requests from a thread and other
threads to multiple banks of shared memory;
servicing a request of the thread to one of the banks; and
scheduling one or more remaining requests of the thread
to other banks before scheduling requests of the other threads
while the request is in-progress, wherein the thread is in-
progress whenever a memory access request from that thread to
the shared memory is currently being serviced.
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Appeal2014-008214
Application 11/835,435
Rejections
Claims 1, 10, 12, 14, 15, 17, 18, and 20 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Nesbit2 and Davis3. (Final Act. 3-9.)
Claims 3-5, 9, 13, 16, and 19 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Nesbit, Davis, and Zhu.4 (Final Act. 9-15.)
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner errs (App. Br. 5-15; Reply Br. 1-7). We
address the issues raised by Appellants' arguments in tum.
Claims 1, 3-5, 9, 10, and 20
Appellants argue the Examiner errs in finding Davis's "active" thread
is the same as the "in-progress" thread recited in claim 1. (App. Br. 7-8.)
We agree. As recited in claim 1, a thread is "in-progress" whenever a
memory access request from that thread to the shared memory is currently
being serviced. Thus, in the claim, the status of a thread depends on the
status of its memory access requests. In contrast, Davis treats a thread as
"active" when it is currently being executed by the CPU. (See Davis i-fi-1 30,
43.) Appellants point out that an "in-progress" thread (i.e., one with a
memory access request currently being serviced) could be either an active
2 Kyle J. Nesbit et al., Fair Queuing Memory Systems, Proceedings of the
39th Annual IEEE/ ACM International Symposium on Microarchitecture
(2006).
3 US 2005/0022196 Al, published Jan. 27, 2005.
4 Zhichun Zhu & Zhao Zhang, A Performance Comparison of DRAM
Memory System Optimizations for SMT Processors, Proceedings of the 1 Ph
Int'l Symposium on High-Performance Computer Architecture (2005).
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Appeal2014-008214
Application 11/835,435
thread or an idle thread as defined in Davis, depending on whether it is
currently being processed by the CPU. (App. Br. 7-8.) Thus, "in-progress,"
as recited in the claim, is not coterminous with Davis's use of the term
"active" to describe a thread.
The Examiner finds that, because Davis gives first priority to an active
thread, first priority is given to an "in-progress" thread when the active
thread is also in-progress as defined in the claim. (See Ans. 6.) We agree,
but this finding does not establish that Davis's active thread is always
considered "in-progress," and claim 1 requires that the system be set up such
that all requests from an in-progress thread are scheduled before requests of
other threads that are not in-progress. The Examiner has not persuasively
rebutted Appellants' contention (App. Br. 8) that, contrary to claim 1,
Davis's system allows for a thread that is not in-progress to take priority
over an in-progress thread when the request currently being serviced is for
an idle thread (see Davis ,-r 21) and a memory access request comes in for an
active thread. (See Davis ,-r 49 ("[I]f multiple processors request access to
the instruction memory at the same time, the instruction fetch requests for
active threads will always be given precedence over those for idle threads,
even if the request from an idle thread comes in earlier.").)
In view of the foregoing, on this record, we do not sustain the
rejection of claim 1under35 U.S.C. § 103(a). For the same reasons, we do
not sustain the rejection of independent claim 20, which is rejected on the
same basis, or the rejections of dependent claims 3-5, 9, and 10.
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Appeal2014-008214
Application 11/835,435
Claims 12-19
We are not persuaded by Appellants' arguments as to claims 12-19.
For these claims, we adopt as our own the findings and reasons set forth by
the Examiner in the action from which this appeal is taken and set forth in
the Answer (see Ans. 3-9). We highlight and address specific arguments
and findings for emphasis as follows.
Claim 12 is a method claim that recites, among other things, steps of
servicing a request of a thread and scheduling one or more remaining
requests of the thread to other banks before scheduling requests of the other
threads while the request is in-progress. Appellants argue the Examiner errs
in rejecting claim 12 for the same reasons argued in support of claim 1.
(App. Br. 9-12.) Unlike system claim 1, however, claim 12 is practiced
whenever a thread with a request currently being executed has requests
scheduled before requests of other threads. As noted by the Examiner (Ans.
5), Appellants admit that "requests from either of Davis' thread types can be
said to be 'in-progress' when they are being executed" (App. Br. 8). Thus,
Davis contemplates the situation where a thread with a request being
serviced (i.e., in-progress), is active and, therefore, will take priority over
other threads with pending memory access requests. (See Davis i-f 49.)
Accordingly, we agree with the Examiner that Davis teaches scheduling one
or more remaining requests of the thread to other banks before scheduling
requests of the other threads while the request is in-progress, as recited in
claim 12.
For the reasons discussed above and by the Examiner, we are not
persuaded the Examiner errs in rejecting claim 12 under 35 U.S.C. § 103(a)
as unpatentable over Nesbit and Davis. Thus, we sustain the rejection of
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Appeal2014-008214
Application 11/835,435
claim 12, and, for the same reasons, the rejections of claims 13-19, which
are not argued separately (see App. Br. 5).
DECISION
We affirm the Examiner's decision to reject claims 12-19. We
reverse the Examiner's decision to reject claims 1, 3-5, 9, 10, and 20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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