Ex Parte MouliDownload PDFPatent Trial and Appeal BoardJun 12, 201713925471 (P.T.A.B. Jun. 12, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/925,471 06/24/2013 Chandra Mouli 08-0302.01 (MICS:0272-1) 1097 52142 7590 06/14/2017 FLETCHER YODER (MICRON TECHNOLOGY, INC.) P.O. BOX 692289 HOUSTON, TX 77269-2289 EXAMINER YEUNG LOPEZ, FEIFEI ART UNIT PAPER NUMBER 2899 NOTIFICATION DATE DELIVERY MODE 06/14/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@fyiplaw.com manware@fyiplaw.com Strickland @ fyiplaw. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte CHANDRA MOULI1 Appeal 2016-000837 Application 13/925,471 Technology Center 2800 Before DONNA M. PRAISS, CHRISTOPHER C. KENNEDY, and MICHAEL G. McMANUS, Administrative Patent Judges. KENNEDY, Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s decision to reject claims 1—26. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. BACKGROUND The subject matter on appeal relates to semiconductor devices. E.g., Spec.212; Claim 1. Claim 1, which is illustrative of the subject matter on 1 According to the Appellant, the real party in interest is Micron Technology, Inc. App. Br. 2. 2 The Examiner cites paragraph numbers from the pre-grant publication of the Specification of the application on appeal, and the Appellant cites both the pre-grant publication and the Specification as filed. All citations to “Spec.” in this decision refer to the Specification filed June 24, 2013. Appeal 2016-000837 Application 13/925,471 appeal, is reproduced below from page 12 (Appendix of Claims on Appeal) of the Appeal Brief (emphasis added to disputed limitation): 1. A transistor comprising: a substrate comprising a source and a drain, wherein the substrate comprises a semiconductor directly on top of an insulator forming an interface, and wherein the insulator is doped; a doped channel formed in the semiconductor between the source and the drain, the channel configured to pass current between the source and the drain, wherein the semiconductor is doped by out diffusion from the insulator such that an ion concentration in the semiconductor is highest at the interface with the insulator, and a highest ion concentration in the insulator is no higher than the ion concentration in the semiconductor at the interface with the insulator, a gate formed directly on the channel; and dielectric spacers located on each side of the gate, wherein the source and the drain are spatially separated from the gate so that the gate is not located over the source and drain. ANALYSIS Claims 1—26 stand rejected under 35 U.S.C. § 112,11, for failure to comply with the written description requirement.3 The Examiner separately addresses independent claims 1 and 21 in the Final Action, which we discuss below. 3 In the Answer, the Examiner suggests that claims 27 and 29—31 stand rejected, see Ans. 2, but provides no discussion of those claims, see id. at 3— 5. Claims 27 and 29—31 were allowed in the Final Action. Final Action dated Dec. 30, 2014, at Office Action Summary, 5. Accordingly, claims 27 and 29-31 are not subject to this appeal. 2 Appeal 2016-000837 Application 13/925,471 Claim 1. Claim 1 is reproduced above. The Examiner determines that the limitation “an ion concentration in the semiconductor is highest at the interface with the insulator, and a highest ion concentration in the insulator is no higher than the ion concentration in the semiconductor at the interface with the insulator” lacks written description support. The Examiner finds: Since fig. 9 does not show the dopant profile of the entire semiconductor layer nor of the entire insulator (notice the top surface of the semiconductor and the bottom surface of the insulator are not shown), but shows only the dopant profile around the semiconductor/insulator interface, the skilled in the art would not have been able to tell where the highest dopant concentration was located. Ans. 4 (emphases in original). The Examiner further finds that 134 of the Specification “teaches the dopant profile of fig. 9 to be an intermediate product,” and that the “original disclosure never teaches the dopant profile after the out-diffusion process.” Id. at 4—5. We are not persuaded by the Examiner’s rationale. Paragraph 34 explains that, “[ajfter the insulators 94 and 96 have been doped, subsequent processing steps that form the JFET structure over the insulator cause the dopants to out diffuse into the semiconductor.” Spec. 134 (emphasis added) (citing arrows 98 in Figs. 7 and 8 as illustrating the out-diffusion process). The Specification then describes the out-diffusion process, referring to Figure 9, which is reproduced below: 3 Appeal 2016-000837 Application 13/925,471 Figure 9 “illustrates the out diffusion of the dopant ions into the semiconductor from the insulator.” Id. More specifically, Figure 9 depicts dopant concentration 100 and the interface 102 between the insulator and the semiconductor. Id. 134, Fig. 9. The figure shows a constant dopant concentration in the insulator and portion of the semiconductor immediately adjacent the interface 102 (i.e., immediately to the left of line 102), and then a decrease in dopant concentration in portions of the semiconductor further from interface 102. We recognize that 134 subsequently states, “[a]s mentioned above, subsequent processing steps which include application of heat to the structure, cause the dopants to out diffuse into the semiconductor.” See Ans. 4—5 (quoting Spec. 134). However, contrary to the Examiner’s assertion, that sentence does not suggest that additional “subsequent processing steps” take place after a device having the doping profile of Figure 9 is already formed. Rather, the words “as mentioned above” indicate that the remainder of the sentence refers back to the earlier sentence in 134 that states, “[ajfter the insulators 94 and 96 have been doped, subsequent processing steps that form the JFET structure over the insulator cause the dopants to out diffuse into the semiconductor.” Spec. 134 (emphasis added). Immediately 4 Appeal 2016-000837 Application 13/925,471 following that sentence, the Specification describes Figures 7—9, which show the out diffusion (Figs. 7 and 8) and the dopant concentration profile after out diffusion has occurred (Fig. 9). Thus, it is clear that the “subsequent processing steps” are subsequent to doping of the insulator; not subsequent to formation of a device having the doping profile of Figure 9. Accordingly, we are not persuaded that a person of ordinary skill in the art would have understood 134 to be suggesting that Figure 9 depicts the dopant profile of an intermediate product. Turning to whether Figure 9 and 134 of the Specification provide written description support for the disputed limitation, we determine that the Examiner has not adequately established that they do not. Cf. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the prior art or on any other ground, of presenting a prima facie case of unpatentability.”). The Examiner does not persuasively explain why a person of ordinary skill in the art would have understood Figure 9 to be showing only a partial doping profile of the insulator and the semiconductor.4 Although the Examiner finds that one “skilled in the art 4 The Appellant’s argument that the Examiner’s rejection relies on “subject matter not claimed” because “Appellant is not claiming the dopant profile of the entire semiconductor” is unpersuasive. See App. Br. 8 (some emphasis added). In reciting “an ion concentration in the semiconductor is highest at the interface with the insulator, and a highest ion concentration in the insulator is no higher than the ion concentration in the semiconductor at the interface with the insulator” (emphases added), claim 1 necessarily implicates the dopant concentration of the entire semiconductor. See Ans. 5—6. The Examiner does not interpret the Appellant’s argument to be an admission that Figure 9 depicts only a partial dopant profile, but nevertheless finds that the dopant profile of the “entire semiconductor is not known.” Id. (emphasis in original). 5 Appeal 2016-000837 Application 13/925,471 would not have been able to tell where the highest dopant concentration was located,” Ans. 4, it appears from Figure 9 that the insulator has a constant dopant concentration, and that the flat horizontal portion of line 100 towards the top of Figure 9 represents the highest dopant concentration, see Spec. Fig. 9. That concentration is depicted as the concentration present throughout the insulator and at the interface 102 of the insulator and the semiconductor. See Spec. Fig. 9. Thus, Figure 9 depicts “an ion concentration in the semiconductor [that] is highest at the interface with the insulator,” and it also depicts “a highest ion concentration in the insulator [that] is no higher than the ion concentration in the semiconductor at the interface with the insulator,” as claimed. That figure and the accompanying text in 134 “reasonably convey[] to those skilled in the art that the inventor had possession of the claimed subject matter.” See Ariad Pharms., Inc. v. EliLilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010). Even to the extent that Figure 9 “does not show the dopant profile of the entire semiconductor layer nor of the entire insulator,” see Ans. 4 (emphases in original), we find the Examiner’s rationale to be unpersuasive. The Examiner’s rejection rests on an assumption that the dopant concentration line 100 beyond the left and/or right edges of Figure 9 spikes to a higher concentration than the highest concentration that is depicted in Figure 9. However the Examiner does not direct us to any evidence or adequately explain why a person of ordinary skill in the art would not have understood the flat horizontal portion of line 100 in Figure 9 to be the peak dopant concentration even if the dopant concentration line did extend further to the left or right beyond what is shown in Figure 9. In the absence of such evidence or explanation, we are not persuaded that a person of ordinary skill 6 Appeal 2016-000837 Application 13/925,471 in the art would have understood the dopant concentration to increase beyond the concentration at the interface of the semiconductor and insulator. Accordingly, on this record, we find that Figure 9 reasonably conveys to a person of ordinary skill that the insulator has a constant dopant concentration and that the dopant concentration decreases in regions of the semiconductor that are further from the interface. See Spec. Fig. 9. The Examiner has not established by a preponderance of the evidence that claim 1 lacks written description support. We reverse the § 112,11 rejection of claim 1. Independent claims 8 and 14 include limitations similar to the disputed limitation of claim 1 discussed above. The Examiner’s rejection of those claims relies on the same analysis described above. See Ans. 4—5. Accordingly, we also reverse the Examiner’s rejection of claims 8 and 14 for the reasons stated above. Claims 2—7, 9-13, and 15—20 depend, directly or indirectly, from claim 1, 8, or 14. The Examiner provides no additional rationale for the rejection of those claims. Accordingly, we also reverse the Examiner’s rejection of those claims for the reasons discussed above. Claim 21. Claim 21 is reproduced below from page 15 (Appendix of Claims on Appeal) of the Appeal Brief (emphasis added to disputed limitation): 21. A semiconductor device comprising: a first level of one or more transistors, the first level comprising: a first insulative substrate; a first semiconductor formed over the substrate; 7 Appeal 2016-000837 Application 13/925,471 a first gate formed directly on the first semiconductor, wherein the first gate and the first semiconductor form a p-n junction; and first insulative spacers formed on each side of the gate; and a second level comprising one or more transistors, the second level comprising: a second insulative substrate formed over the first level; a second semiconductor formed over the second substrate; a second gate formed directly on the second semiconductor, wherein the second gate and the second semiconductor form a p-n junction; and second insulative spacers formed on each side of the second gate, wherein each of the first and second semiconductors comprise a respective source, a drain, and a channel, wherein the source and drain of the first and second semiconductors are separated from their corresponding gates a distance approximately 1/3 the length of the corresponding gates, and wherein the second gates of p-type and n-type transistors of the second level are shorter than the first gates of the transistors of the first level. The Examiner finds that the original disclosure does not provide written description support for the limitation “the second gates of p-type and n-type transistors of the second level are shorter than the first gates of the transistors of the first level” because “the original disclosure does not teach both p-type and n-type transistors to be formed in the second level.” Ans. 5. Paragraph 36 of the Specification describes multi-level semiconductor devices comprising JFET structures on each level. See Spec. 136. While it 8 Appeal 2016-000837 Application 13/925,471 teaches that “[t]he JFET structures of the first level 110 may include n-type JFETs and the second level 112 may include p-type JFETs,” it expressly teaches that “other configurations are also contemplated.” Id. (emphasis added). The Appellant argues that the “other configurations” language “indicates that the second level may include both p-type JFETs and n-type JFETs. If only a p-type or an n-type JFET could be used on the first and second levels, then there would be only one other configuration that could be contemplated regarding the configuration of the JFET structures in FIG. 9 in contrast to the explicit disclosure of the specification.” App. Br. 10. In the Answer, the Examiner responds that the “Appellant is not entitled to a patent to a device that the skilled in the art could have conjured up, but without Appellant’s disclosing what the device is.” Ans. 7. We are not persuaded by the Examiner’s reasoning. “The invention claimed does not have to be described in ipsis verbis in order to satisfy the description requirement of § 112.” In re Lukach, 442 F.2d 967, 969 (CCPA 1971); see also Union Oil Co. of Cal. v. Atlantic Richfield Co., 208 F.3d 989, 1000 (Fed. Cir. 2000). It need only be described in terms that “reasonably convey[] to those skilled in the art that the inventor had possession of the claimed subject matter.” Ariad, 598 F.3d at 1351. Here, as the Appellant explains, a person of ordinary skill would have understood that two types of JFETs are known: p-type and n-type. See, e.g., Spec. 136; App. Br. 10. The Specification states that “the second level 112 may include p-type JFETs,” and it further states that “other configurations are also contemplated.” See Spec. 136 (emphasis added). A person of ordinary skill in the art would have understood that the only “other configurations” possible are n-type JFETs alone or a combination of p-type 9 Appeal 2016-000837 Application 13/925,471 and n-type JFETs. Given that 136 uses the word “may,” rather than “must,” to describe the second level’s inclusion of p-type JFETs, and that 136 expressly discloses “other configurations” which a person of ordinary skill in the art would have understood to encompass a combination of p-type and n-type JFETs, we are not persuaded that claim 21 lacks written description support merely because the Specification does not ipsis verbis describe the disputed claim limitation. See Lukach, 442 F.2d at 969. On this record, the Examiner has not shown by a preponderance of the evidence that the Specification does not “reasonably convey[] to those skilled in the art that the inventor had possession of the claimed subject matter.” See Ariad, 598 F.3dat 1351. Accordingly, we reverse the Examiner’s rejection of claim 21. The Examiner provides no additional rationale for the rejection of claims 22—26, which depend, directly or indirectly, from claim 21. We therefore also reverse the Examiner’s rejection of claims 22—26. CONCLUSION We REVERSE the Examiner’s rejection of claims 1—26. REVERSED 10 Copy with citationCopy as parenthetical citation