Ex Parte MouliDownload PDFPatent Trial and Appeal BoardMay 2, 201813604355 (P.T.A.B. May. 2, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/604,355 09/05/2012 Chandra Mouli 52142 7590 05/04/2018 FLETCHER YODER (MICRON TECHNOLOGY, INC.) P.O. BOX 692289 HOUSTON, TX 77269-2289 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 08-0304.01 MICS:0274-l 2375 EXAMINER LIU, BENJAMIN T ART UNIT PAPER NUMBER 2893 NOTIFICATION DATE DELIVERY MODE 05/04/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): docket@fyiplaw.com manware@fyiplaw.com s trickland @fyiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte CHANDRA MOULI Appeal2017-006631 Application 13/604,355 Technology Center 2800 Before CATHERINE Q. TIMM, GEORGE C. BEST, and JENNIFER R. GUPTA, Administrative Patent Judges. GUPTA, Administrative Patent Judge. DECISION ON APPEAL 1 Appellant2 appeals under 35 U.S.C. § 134(a) from the final decision rejecting claims 1-8 and 11-25. We have jurisdiction under 35 U.S.C. § 6(b ). We AFFIRM-IN-PART. 1 In this Decision, we refer to the Specification filed September 5, 2012 ("Spec."), the Final Office Action dated March 24, 2016 ("Final Act."), the Appeal Brief filed August 23, 2016 ("Appeal Br."), the Examiner's Answer dated January 18, 2017 ("Ans."), and the Reply Brief filed March 20, 2017 ("Reply Br."). 2 Appellant identifies the real party in interest as Micron Technology, Inc. Appeal Br. 2. Appeal2017-006631 Application 13/604,355 The subject matter of the claims on appeal relates to methods for manufacturing semiconductor devices, specifically junction field-effect transistor (JFET) device structures. See Spec. i-fi-12, 37--45; see also Appellant's application Figs. 5-7. Claims 1, 11, 15, and 23, reproduced below from the Claims Appendix of the Appeal Brief, are illustrative of the claims on appeal. 1. A method of manufacturing comprising: forming a diffusion based isolation region to electrically isolate a plurality of JFETaccess devices; forming a channel region of a JFET access device of the plurality of JFET access devices in an area created by the diffusion based isolation region; forming a gate of the JFET access device over and in physical contact with the channel region; and forming a memory element in the same plane as the gate or in a plane above the gate. App. Br. 2 7 (Claims App.) 11. A method of manufacturing comprising: forming a diffusion based isolation region to electrically isolate a plurality of JFET access devices, the diffusion based isolation region comprising: Id. at 28. forming trenches less than 300 Angstroms deep; filling the trenches with a material having a higher bandgap than silicon; forming a thermal oxide over the high bandgap material; and diffusing ions into the thermal oxide. 2 Appeal2017-006631 Application 13/604,355 15. A method of manufacturing comprising: forming a Fin channel region of a JFET access device in a semiconductor substrate; forming a gate of the JFET access device directly over the Fin channel region; and forming a capacitive memory element electrically coupled to the JFET access device. Id. at 29. 23. A method of manufacturing comprising: forming a Fin channel region; forming a gate directly on the surface of the Fin channel region, wherein the gate extends from the Fin channel region only in an x-direction; and forming an elevated source region and an elevated drain region on the Fin channel region, wherein the elevated source region and the elevated drain region extend above the Fin channel region and above the gate only in a z-direction, and wherein the z-direction is substantially perpendicular to the x- direction and to the substrate, and the x-direction is substantially parallel to the substrate. Id. at 30. REJECTIONS The Examiner maintains the following rejections on appeal: Rejection 1: Claims 15, 16, 19, and 21 under pre-AIA 35 U.S.C. § 102(e) as anticipated by Boyle (US 2009/0057728 Al, published March 5, 2009) (Final Act. 2-3); Rejection 2: Claims 1, 4, 5, and 8 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Seacrist et al. (US 4,939,099, issued July 3, 1990) ("Seacrist") (Final Act. 3-5); 3 Appeal2017-006631 Application 13/604,355 Rejection 3: Claim 2 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Seacrist, Mouli (US 2005/0287739 Al, published December 29, 2005), and Miura et al. (US 5,148,247, issued September 15, 1992) ("Miura") (Final Act. 5---6); Rejection 4: Claim 3 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Seacrist in view of Cooper et al. (WO 88/08617, published November 3, 1988) ("Cooper") (Final Act. 6-7); Rejection 5: Claims 6 and 7 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Seacrist in view of Gossner et al. (US 2007 /0040221 A 1, published February 22, 2007) ("Gossner") (Final Act. 7-8); Rejection 6: Claims 11 and 12 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Mouli, Miura, and Seacrist (Final Act. 8-9); Rejection 7: Claims 13 and 14 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Mouli, and Miura (Final Act. 9-1 O); Rejection 8: Claim 17 under 35 U.S.C. § 103(a) as unpatentable over Boyle and Izumida et al. (US 7,662,679 B2, issued February 16, 2010) ("Izumida") (Final Act. 1 O); Rejection 9: Claim 18 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Boyle in view of Kapoor (US 2008/0272407 Al, published November 6, 2008) (Final Act. 10-11); Rejection 10: Claim 20 under 35 U.S.C. § 103(a) as unpatentable over Boyle in view ofMasuoka et al. (US 2004/0262681 Al, published December 30, 2004) ("Masuoka") (Final Act. 11-12); Rejection 11: Claim 22 is rejected under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Boyle in view of Schulz et al. (US 8, 188,551 B2, issued May 29, 2012) ("Schulz") (Final Act. 12); 4 Appeal2017-006631 Application 13/604,355 Rejection 12: Claims 23 and 24 under pre-AIA 35 U.S.C. § 103(a) as unpatentable over Schwerin (US 2005/0151206, published July 14, 2005) in view of Kapoor (Final Act. 12-14); and Rejection 13: Claim 25 under 35 U.S.C. § 103(a) as unpatentable over Schwerin, Kapoor, and Schulz (Final Act. 14). DISCUSSION Rejections 1 & 8-11 We focus our discussion of Rejections 1 and 8-11 on independent claims 15 and 19, which include the argued limitations. Appeal Br. 8-11, 20-22. Independent claim 15' s method of manufacturing includes, inter alia, "forming a Fin channel region of a JFET access device in a semiconductor substrate," and "forming a gate of the JFET access device directly over the Fin channel region." Similarly, independent claim 19's method of manufacturing a JFET access device includes, inter alia, "forming a gate of a JFET access device around Fin channel region of the JFET access device." An annotated version of Figure 7 of Appellant's application, reproduced below, depicts a JFET access device, Fin-JFET 140, having a Fin channel region (144) and a gate (142) formed directly over the Fin channel region (144 ). 5 Appeal2017-006631 Application 13/604,355 gate conductor ('142) 142 140 Fin-JFET device ("140) .¥"' 1/·54 ... 144 Annotated Figure 7 shows an embodiment of Appellant's JFET access device, Fin-JFET structure 140. The Examiner rejects independent claims 15 and 19 under 35 U.S.C. § 102( e) as anticipated by Boyle. Final Act. 2-3. The Examiner bears the initial burden of presenting a prima facie case ofunpatentability. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). To serve as an anticipatory reference, "the reference must disclose each and every element of the claimed invention." In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009). With regard to independent claims 15 and 19, the Examiner finds that Boyle's Figures 3C-3F, for example Boyle's Figure 3D, an annotated version of which is reproduced below, discloses forming Fin channel region 321 of a JFET access device ("a gate wrap JFET 311 ") on semiconductor substrate 358, forming gate 327 of JFET access device 311 directly over and around Fin channel region 321, and forming capacitive memory element 312 electrically coupled to JFET access device 311. Final Act. 2, 3; Boyle iTiT 54--57; Figs. 3C-3F. 6 Appeal2017-006631 Application 13/604,355 channel substrate region (321) gate substrate region {327) gate electrode (329) 327 321 362 FIG. 30 360 Boyle's Figure 3D, annotated, shows an example of a "gate wrap" access JFET 311. Appellant argues that Boyle's gate wrap access JFET 311 is different from a JFET device with a Fin channel region formed in a semiconductor substrate (e.g., Fin-JFET). Appeal Br. 10. Appellant explains that Fin- FETS are three-dimensional structures with the fin forming the source and drain, rising above the substrate. Id. Appellant contends that a person skilled in the art would fully appreciate that Boyle's JFET 311 is not a Fin- JFET (e.g., Fin-JFET 140 illustrated and described with regard to FIG. 7 of Appellant's application reproduced above), and does not disclose forming a fin, much less forming a Fin channel region in a semiconductor substrate of a JFET access device as in claim 15's and 19's methods. Id. Appellant's arguments are persuasive of reversible error. Despite the Examiner's finding, Boyle's channel region 321 does not appear to have a "fin," a three-dimensional structure rising above the substrate. Thus, Boyle does not teach a JFET access device with a Fin channel region as in claims 15 and 19. 7 Appeal2017-006631 Application 13/604,355 In the Answer, the Examiner finds that Boyle discloses that "a gate electrode 329 can extend downward on a side surface of a JFET (as shown by dashed lines)." Ans. 2; Boyle i-f 55, Fig. 3D. The Examiner finds that when Boyle's gate electrode 329 is configured in this manner, channel substrate region 3 21 rises above substrate insulator 3 60 forming a fin channel region, and gate electrode 329 is formed on the top and two sidewall surfaces of fin channel substrate region 321. Ans. 2. The Examiner's findings in the Answer are flawed in two respects. First, as discussed above, we disagree with the Examiner's finding that channel region 321 has a "fin," and thus, forms a Fin channel region as in claim 15 and 19' s methods. Additionally, claim 15's method requires forming a gate of the JFET device "directly over" the Fin channel region. Appellant's Specification explains that "directly over" is meant to refer to materials in physical contact, i.e., with no intervening layers. Spec. i-f 44. In the gate wrap JFET depicted in Boyle's Figure 3D, gate substrate region 327 is formed between gate electrode 329 and channel substrate region 321. Thus, even if we were to agree that Boyle's channel region 321 is a "Fin channel region," Boyle's Figure 3D does not teach forming a gate of the JFET access device directly over the Fin channel region, as in claim 15' s method. For the reasons above, the Examiner has not established that Boyle teaches every limitation of claims 15 and 19. Accordingly, we do not sustain the anticipation rejection of claims 15, 16, 19, and 21. The Examiner relies upon the factual findings made in the anticipation rejection to support the obviousness rejection of claims 17, 18, 20, and 22. Final Act. 10-12. Because the anticipation rejection is based on erroneous 8 Appeal2017-006631 Application 13/604,355 factual findings, as discussed above, we do not sustain the obviousness rejections of claims 17, 18, 20, and 22. Rejections 2-5 We focus our discussion of Rejections 2-5 on independent claim 1, which includes the argued limitations. Appeal Br. 12-15. Independent claim 1 's method of manufacturing recites, inter alia, "forming a diffusion based isolation region to electrically isolate a plurality of JFET access devices[,] forming a channel region ... in an area created by the diffusion based isolation region[, and] forming a gate ... over and in physical contact with the channel region." The Examiner finds that Seacrist's Figure 4 discloses forming a diffusion based isolation region ( 46, 36) ("thermal diffusion" (id. 4:38--41 )), forming a channel region (96) in an area created by the diffusion based isolation region ( 46, 36), and forming a gate (94) over an in physical contact with the channel region (96). Final Act. 4--5. Appellant argues that Seacrist does not teach or suggest forming a gate of the JFET device "over and in physical contact with" the channel region, as recited in claim 1 's method. Appeal Br. 12. Appellant's argument is persuasive of reversible error. As Appellant persuasively argues, Seacrist discloses that channel region 96 is formed under top gate region 94. Appeal Br. 13. That is, Seacrist discloses forming top gate region 94, and then subsequently forming channel region 96. Id. (citing Seacrist 5:29--43). In the Answer, the Examiner finds that Seacrist's gate region 94 is not "operational" until the boron dopant that forms channel region 96 is implanted below gate region 94. Ans. 3; Seacrist 5:29--43. Thus, the 9 Appeal2017-006631 Application 13/604,355 Examiner finds that "the completion of the step of implanting the boron dopant ... [in] Seacrist[] is where the step of forming a gate of the JFET access device over and in physical contact with the channel region is completed." Ans. 3. We disagree with the Examiner's findings. Regardless of when Seacrist's gate region 94 is "operational," Seacrist teaches forming top gate region 94, and then subsequently implanting boron dopant below top gate region 94 to form JFET channel region 96. Seacrist 5:29--43. On this record, the Examiner has not established that Seacrist teaches or suggests forming a channel region of a JFET access device, and subsequently forming a gate "over and in physical contact" with the channel region, as in claim 1 's method. As a result, the Examiner has not met the initial burden of setting forth a prima facie case of obviousness for claim 1under35 U.S.C. § 103(a) over Seacrist. The§ 103(a) rejections of claims 2-8 have the same deficiency as the § 103(a) rejection of claim 1. The Examiner does not rely upon the additional prior art references to reject claims 2, 3, 6, and 7 to remedy the deficiencies of Seacrist. Final Act. 5-8. Therefore, we likewise do not sustain the§ 103(a) rejections of claims 2-8. Rejections 6 and 7 We focus our discussion of Rejections 6 and 7 on independent claims 11 and 13. Claim 11 and 13 's methods require, inter alia: forming trenches less than 300 Angstroms deep; filling the trenches with a material having a higher bandgap than silicon; 10 Appeal2017-006631 Application 13/604,355 forming a thermal oxide over the high bandgap material; and diffusing ions into the thermal oxide. Appeal Br. 28 (Claims App.). Appellant's Figure 12, an annotated version of which is reproduced below, depicts an embodiment of a JFET access device having a trench (222) filled with a material having a higher bandgap than silicon (226), and a having a thermal oxide layer (230) over the high bandgap material, as recited in claim 11 and 13 's methods. Annotated Figure 12 illustrates an embodiment of Appellant's diffusion based isolation region 212. The Examiner finds that Mouli' s Figure 2A, an annotated version of which is reproduced below, discloses forming isolation trench 103, filling isolation trench 103 with a material having a higher bandgap than silicon (silicon oxide), and forming thermal oxide 112 over the high bandgap material. Final Act. 8 (citing Mouli i-fi-135-37, Fig. 2A). 11 Appeal2017-006631 Application 13/604,355 trench (103) FIG.2A 105 200 r --' "- 1sulation 9ate (lliJ) aluminum oxid€ layer ( l 12) Annotated Figure 2A shows a cross-sectional view of an exemplary embodiment of Mouli' s memory cell. Regarding the trench depth, the Examiner finds that Mouli discloses that "use of an isolation gate 110 . .. allows the use of a trench 103 having a depth D of less than about 2000 A[,]" and "in some cases, ... may be altogether eliminated with sufficient device isolation being provided solely by the isolation gate formed directed on the substrate surface 100." See Final Act. 8 (citing Mouli i-f 35). Based on this disclosure, the Examiner finds that Mouli teaches forming an isolation trench having a depth ranging from 0 Angstroms to 2000 Angstroms. Ans. 3--4. The Examiner acknowledges that Mouli does not disclose diffusing ions into its thermal oxide layer (112). See Final Act. 8. To account for this 12 Appeal2017-006631 Application 13/604,355 difference, the Examiner finds that Miura' s Figure 6, an annotated version of which is reproduced below, discloses forming diffusion based isolation region 32 to electrically isolate a plurality of devices, where diffusion based isolation region 32 includes diffusing ions into thermal oxide 27. FIG.6 k~yer {32) 40 _ ... _.- .. ' trench {26) Miura' s Figure 6, annotated, shows a cross sectional view of its semiconductor device with an insulator layer 32 having charges trapped therein (trapped charge layer). The Examiner finds that Miura teaches that because of trapped charge layer 32, negative charges are formed in oxide layer 27, and positive charges are induced in the substrate at the portion where trapped charge layer 32 exists. See Final Act. 8-9 (citing Miura 6:1-7). Thus, according to Miura, "it is thus possible to suppress the lateral direction leak current within the same element of the semiconductor device." Miura 6: 1-7. The Examiner finds that one of ordinary skill in the art would have been led to form Mouli' s aluminum oxide layer with the trapped charge layer as taught in Miura "to induce positive charges in the substrate at the portion where the trapped charge layer exists[,] and ... to suppress the 13 Appeal2017-006631 Application 13/604,355 lateral direction leak current with the same element of the semiconductor device." Final Act. 8-9. Appellant argues that Mouli does not enable, or disclose with specificity, a trench region with a depth ranging from 0 to 2000 Angstroms. Appeal Br. 16; Reply Br. 6. Appellant's argument is not persuasive of reversible error. A prior art patent is presumed to be enabled. See, e.g., In re Antor Media Corp., 689 F.3d 1282, 1287-88 (Fed. Cir. 2012). We agree with the Examiner that Mouli discloses that its trench can have a depth of 0 Angstroms to 2000 Angstroms (Mouli i-f 35), and this depth fully encompasses the depth range of "less than 300 Angstroms" recited in method claims 11 and 13. Appellant has not directed us to sufficient evidence to establish that one of ordinary skill in the art would not have been able to make and use an isolation trench having a depth ranging from 0 Angstroms to 2000 Angstroms based on Mouli' s disclosure. Appellant argues that shallow trench isolation (STI) and diffusion based isolation are understood by those skilled in the art as being different types of electrical isolation techniques. Appeal Br. 17-18. Appellant argues that one skilled in the art would not have been motivated to modify aspects of Mouli's STI trench isolation with Miura's diffusion-based isolation technique. Id. at 18. Appellant further contends that Mouli cannot be modified by Miura because the combination "cannot work." Id. Appellant's arguments are not persuasive of reversible error. The Examiner finds, and Appellant agrees, that shallow trench isolation and diffusion-based isolation are two techniques that provide electrical isolation. Compare Ans. 4, with Appeal Br. 18. The Examiner finds that Miura 14 Appeal2017-006631 Application 13/604,355 teaches that trapped charge layer 32 having negative charges formed in oxide layer 27, induces positive charges in substrate 21, and thus, provides electrical isolation-minimizing current leakage in the lateral direction. Ans. 4; Final Act. 8-9 (citing Miura 6:1-7). Appellant does not provide any persuasive argument or direct us to sufficient evidence to refute the Examiner's finding that one of ordinary skill in the art would have been led, based on Miura's teachings, to diffuse negative charges in Mouli's aluminum oxide layer 112, and induce a positive charge in substrate layer 100 in the same way that biasing the aluminum oxide dielectric layer 112 with a slightly negative charge, as disclosed in Mouli, would induce a positive charge in the substrate layer 100 even though a STI region 103 is placed in between. Compare Ans. 4--5, and Mouli i-fi-131, 34, with Reply Br. 5---6; see also Mouli i149 (teaching that Mouli's isolation region can be used with "other isolation structures and techniques"). Because Appellant has not identified error in the Examiner's obviousness rejection of claim 11, we sustain the rejection of claims 11 and 12. Appellant does not present separate arguments for the patentability of claims 13 and 14, but instead rely on the same arguments discussed above in regards to independent claim 11. Appeal Br. 20. Thus, we also sustain the obviousness rejection of claims 13 and 14. Rejections 12 and 13 We focus our discussion of Rejections 12 and 13 on independent claim 23, which includes the argued limitations. Appeal Br. 22-25. 15 Appeal2017-006631 Application 13/604,355 Independent claim 23 's method of manufacturing recites, inter alia: forming a Fin channel, forming a gate directly on the surface of the Fin channel region, wherein the gate extends from the Fin channel region only in an x-direction, and forming an elevated source region and an elevated drain region on the Fin channel region, wherein the elevated source region and the elevated drain region extend above the Fin channel region and above the gate only in a z-direction ... wherein the z-direction is substantially perpendicular to the x- direction and to the substrate, and the x-direction is substantially parallel to the substrate. Appeal Br. 30 (Claims App.) (emphasis added). An embodiment of Appellant's JFET device having an elevated source region and an elevated drain region are depicted in an annotation of Appellant's Figure 10, reproduced below. 16 Appeal2017-006631 Application 13/604,355 Fin device (170) elevated source region i172) Fin channel region ("176) 170~ gate (178) elevated drain region (174) z- direction Annotated Figure 10 illustrates an embodiment of Appellant's Fin- JFET that includes an elevated source region (172) and elevated drain region (174). The Examiner finds that Schwerin's Figure 2, an annotated version of which is reproduced below, discloses forming Fin 17 of channel region 15, gate 2 extending from Fin channel region 15 only in an x-direction (horizontal direction), and forming elevated source region 12 and elevated drain region 13 on Fin channel region 15. Final Act. 12-13 (citing Schwerin Figure 2). 17 Appeal2017-006631 Application 13/604,355 FIG 2 98 drain mginn { ! 3) \,.._a , ! 18 13 /0 Schwerin's Figure 2, annotated, shows in the left illustration, a cross section through transistor structure 98, and in the right illustration, a perpendicular cross section of transistor 98. The Examiner finds that Schwerin teaches that elevated source region 12 and elevated drain region 13 extend "above the Fin channel region 15 and above ... gate 2 only in a z-direction (vertical direction)." Id. at 13 (citing Schwerin i-f 20 ("gate electrode has at least one section that extends in the x axis between the two source/drain regions and in the vertical direction from the lower edges of the source/drain regions to beyond a lower edge of the recess structure.")). Appellant argues that gate 2 in Schwerin's Figure 2 "clearly extends to at least a top portion of the source region 12 and drain region 13." Appeal Br. 23. Thus, Appellant contends that Schwerin does not teach or suggest forming an elevated source region and an elevated drain region that "extends above ... the gate region only in a z-direction," as recited in claim 23 's method. Id. 18 Appeal2017-006631 Application 13/604,355 In the Answer, the Examiner explains that the right-hand illustration of Schwerin' s Figure 2 only shows the cross section along line B in the left hand illustration of Schwerin's Figure 2, which cuts along the area within the recess trench 18, and not within the area of source region 12 and drain region 13. Ans. 5. The Examiner finds that Schwerin's Figure 3B, an annotated version of which is reproduced below, provides a better illustration of the configuration of Schwerin' s gate and source and drain regions. Id. at 5---6. FIG 38 61 12,13 2 3 2 3 gate etec~rmie (2: : Annotated Figure 3B shows the structure and functioning of Schwerin' s memory cell. The Examiner finds that Schwerin's Figure 3B show that source and drain regions 12, 13 extend above a recessed portion of gate electrode 21 only in a z-direction. Ans. 6; Schwerin i-f 104. 19 Appeal2017-006631 Application 13/604,355 In the Reply Brief, Appellant argues that Schwerin's Figure 3B "clearly shows that the source/drain regions (12, 13) do not extend above the electrode (21) (i.e., the entire electrode including its upper most portion)." Reply Br. 8. Appellant's argument is persuasive of reversible error. We agree with the Appellant that neither Schwerin's Figure 2 nor Figure 3B shows forming the source and drain regions extending above the gate electrode only in a z- direction (vertical direction) as required by claim 23 's method. The Examiner does not rely on Kapoor to remedy this deficiency of Schwerin. Final Act. 13-14; Ans. 5---6. As a result, the Examiner has not met the initial burden of setting forth a prima facie case of obviousness for claims 23 and 24 under 35 U.S.C. § 103(a) over Schwerin and Kapoor. The§ 103(a) rejection of claim 25 has the same deficiency as the § 103(a) rejection of claims 23 and 24. The Examiner does not rely on the additional prior art references to reject claim 25 to remedy the deficiency in Schwerin. Final Act. 14. Therefore, we likewise do not sustain the§ 103(a) rejection of claim 25. DECISION The rejection of claims 15, 16, 19, and 21under35 U.S.C. § 102(e) as anticipated by Boyle is reversed. The rejections of claims 17, 18, 20, and 22 under 35 U.S.C. § 103(a) as unpatentable over Boyle in view of additional prior art references are reversed. The rejection of claims 1, 4, 5, 8 under 35 U.S.C. § 103(a) as unpatentable over Seacrist is reversed. 20 Appeal2017-006631 Application 13/604,355 The rejections of claims 2, 3, 6, and 7 under 35 U.S.C. § 103(a) as unpatentable over Seacrist in view of additional prior art references are reversed. The rejection of claims 11 and 12 under 35 U.S.C. § 103(a) as unpatentable over Mouli, Miura, and Seacrist is affirmed. The rejection of claims 13 and 14 under U.S.C. § 103(a) as unpatentable over Mouli, and Miura is affirmed. The rejection of claims 23 and 24 under 35 U.S.C. § 103(a) as unpatentable over Schwerin in view of Kapoor is reversed. The rejection of claim 25 under 35 U.S.C. § 103(a) as unpatentable over Schwerin, Kapoor, and Schulz is reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED-IN-PART 21 Copy with citationCopy as parenthetical citation