Ex Parte Morris et al

Board of Patent Appeals and Interferences

Jan 10, 2012

10909057 (B.P.A.I. Jan. 10, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DALE MORRIS and ROBERT S. SCHREIBER
____________

Appeal 2009-010830
Application 10/909,057
Technology Center 2100
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Before LANCE LEONARD BARRY, JEAN R. HOMERE, and THU ANN
DANG, Administrative Patent Judges.

BARRY, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
The Patent Examiner rejected claims 1-36. The Appellants appeal
therefrom under 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C.
§ 6(b).

Appeal 2009-010830
Application 10/909,057

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INVENTION
The Appellants describe the invention at issue on appeal as follows.
The present invention provides for performance
improvements in the context of write-back caches by keeping
track of modified valid data that has been "spent". "Spent" data
is data that was useful, but is no longer as its purpose has been
served, just as a spent battery is no longer useful. . . . [N]ot
writing back spent data reduces main memory accesses and thus
improves performance.
(Appeal Br. 8.)
ILLUSTRATIVE CLAIM
36. A system for providing to a processor copies of data
in a cache having plural cache lines for containing data, said
cache further including means for indicating for each of said
cache lines whether or not it contains valid data having spent
status.
REJECTIONS
Claim 36 stands rejected under 35 U.S.C. § 102(b) as being
anticipated by U.S. Patent No. 6,349,365 B1("McBride").
Claims 1-35 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over McBride and U.S. Patent No. 6,886,085 B1 ("Shuf").

DISCUSSION
We will decide the appeal of independent claim 36 individually.
Based on the dependencies of the claims, we will decide the appeal of
claims 1-35 on the basis of independent claims 1, 6, 17, and 25. Therefore,
the issue before us follows.
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Application 10/909,057

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Did the Examiner err in finding that McBride discloses a cache having
at least one cache line for storing data, as required by independent claims 1,
6, 17, 25, and 36?
The Examiner makes the following finding.
McBride's cache containing instructions, in fact contains data
and meets the requirements of claim 36 of "cache lines for
containing data" as ["instruction cache 16 is configures to store
up to 64 kilobytes of instructions in a 4 way set associative
structure having 32 byte lines (a byte comprises 8 binary bits)"
(Col. 5, lines 60-67)].
(Ans. 18-19.)1
"'It is axiomatic that, in proceedings before the [Patent and Trademark
Office], claims in an application are to be given their broadest reasonable
interpretation consistent with the specification, [ ] and that claim language
should be read in light of the specification as it would be interpreted by one
of ordinary skill in the art.'" In re Bond, 910 F.2d 831, 833 (Fed. Cir. 1990)
(quoting In re Sneed, 710 F.2d 1544, 1548 (Fed. Cir. 1983) (citations
omitted).)
Here, the Specification explains that "[a] computer system typically
includes memory for storing data and program instructions and a processor
for manipulating data in accordance with the program instructions." (Spec.

1 Although the Examiner mentions "The Authoritative Dictionary of IEEE
Standard Terms" (Ans. 18), the publication date of the Dictionary and the
relevant page are omitted from the Examiner's mention. Furthermore, no
copy of the relevant page is attached to the Answer. The Examiner should
ensure that all pending and future reliance on dictionaries includes a
complete citation thereto and a copy of the relevant part of the dictionaries.

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Application 10/909,057

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1.) We find such an explanation distinguishes instruction from data,
contrary to the Examiner’s finding that instructions are data.
We likewise find that McBride distinguishes instruction from data.
More specifically, the reference discloses that an "area of concern for the
designer is when to overwrite or invalidate existing instructions and data in
a cache to make room for new instructions and data." (Col. 2, ll. 8-11
(emphases added.)) Based on our findings, we agree with the Appellants
that "[i]t would thus be clear to one skilled in the art having read the
specification [and McBride] that 'data' as used in the claims does not
encompass instructions." (Reply Br. 5.)
The Examiner does not allege, let alone show, that the addition of
Shuf cures the aforementioned deficiency of McBride. Furthermore, we
agree with the Appellants' following argument.
In a typical computer system, data in a data cache can be
modified so as to render the corresponding data in main
memory invalid, while instructions in an instruction cache are
not modified so as to make corresponding instructions in main
memory invalid. Thus, data in a data cache must be written
back to update main memory, while instructions in an
instruction cache do not have to be written back to update main
memory. Accordingly, there is a motivation for providing
write-back capability in a data cache, but not, in general, for an
instruction cache. Nothing in Shuf suggests anything different.
(Reply Br. 10.)
Therefore, we conclude that the Examiner erred in finding that
McBride discloses a cache at least one cache line for storing data, as
required by independent claims 1, 6, 17, 25, and 36.

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Application 10/909,057

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DECISION
We reverse the rejections of claims 1, 6, 17, 25, and 36 and of claims
2-5, 7-16, 18-24, and 26-35, which depend therefrom.

REVERSED

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