Ex Parte Mobin et al

Patent Trial and Appeal Board

Dec 10, 2012

11095770 (P.T.A.B. Dec. 10, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/095,770 03/31/2005 Mohammad S. Mobin Mobin 48-7-46-8 2501
47386 7590 12/10/2012
RYAN, MASON & LEWIS, LLP
1300 POST ROAD
SUITE 205
FAIRFIELD, CT 06824
EXAMINER
KASSA, ZEWDU A
ART UNIT PAPER NUMBER
2632
MAIL DATE DELIVERY MODE
12/10/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MOHAMMAD S. MOBIN, GREGORY W. SHEETS,
LANE A. SMITH, and CRAIG B. ZIEMER
____________

Appeal 2010-006301
Application 11/095,770
Technology Center 2600
____________

Before MAHSHID D. SAADAT, ERIC S. FRAHM,
and TREVOR M. JEFFERSON, Administrative Patent Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-006301
Application 11/095,770

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Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1-20, which are all the claims pending in this application. We
have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Introduction
Appellants’ invention relates to techniques for clock and data
recovery and improving the linearity of phase interpolators (see Spec. 1:5-7).
Exemplary Claim
Independent claim 1 is exemplary of the claims under appeal and
reads as follows:
1. A method for linearizing a phase interpolator,
comprising:
obtaining a mapping of up to 2
N
desired phase values to a
corresponding M bit value, where M is greater than N; and
applying a corresponding M bit value to said phase
interpolator to obtain a desired one of said 2
N
desired phase
values.

The Examiner’s Rejections
Claims 1, 3, 4, 6, 7, 8, 9, 11, 12, 14-16, 18, and 19 stand rejected
under 35 U.S.C. § 102(e) as anticipated by Tell (US 2006/0140321 A1).
Claims 2, 10, and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tell and Garlepp (US 6,133,773).
Claims 5, 13, and 20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tell and Nakamura (US 2002/0036526 A1).
Appeal 2010-006301
Application 11/095,770

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Appellants’ Contentions
With respect to independent claims 1, 8, and 15, Appellants contend
that the Examiner erred in rejecting the claims as anticipated by Tell because
the cited portions of the reference do not teach “linearizing a phase
interpolator, comprising: obtaining a mapping of up to 2
N
desired phase
values to a corresponding M bit value, where M is greater than N; and
applying a corresponding M bit value to said phase interpolator to obtain a
desired one of said 2
N
desired phase values” (App. Br. 6) (emphases in
original). Appellants specifically assert that “Tell does not map bit values of
different lengths at all” (App. Br. 3). Appellants compare a representative
illustration of Tell’s teaching in paragraphs 2 and 25 (see App. Br. 4) with
the lower section of Figure 5 of instant application (see App. Br. 5) to argue
the differences between Tell’s disclosure and the recited features of claim 1.
Appellants rely on similar arguments in support of the patentability of
independent claims 2, 10, and 17 (App. Br. 6-7), allowing these claims to
fall with claim 1.

ISSUE
Based on Appellants’ arguments in the briefs, the principal and
dispositive issue presented in this appeal is as follows:
Has the Examiner erred in rejecting the claims as being anticipated by
Tell because the reference does not teach all the recited features of claim 1?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
Appeal 2010-006301
Application 11/095,770

4
conclusion. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken and (2) the
rebuttals to arguments expressed by the Examiner in the Examiner’s Answer
in response to Appellants’ Appeal Brief (see Ans. 17-20).
We specifically agree with the Examiner (Ans. 6), that the cited
portion in paragraph 25 of Tell discloses N-bit and M-bit phase values as 3-
bit vector select field and 6-bit interpolation control field where up to 8 or
2
N=3
phase values are generated (Ans. 17-18). We further observe that
Appellants’ arguments, which are further repeated in their Reply Brief, are
based on an illustration of Appellants’ interpretation of Tell’s disclosure
rather than specifically addressing the Examiner’s position. Furthermore,
we see no correspondence between Appellants’ discussion of the present
invention with reference to their Figure 5 (App. Br. 4-5; Reply Br. 3-4) and
the appealed claims.
We also agree with the Examiner’s analysis of Garlepp and Nakamura
to conclude that the subject matter of claims 2, 5, 10, 13, 17, and 20 is taught
or suggested by the combination of these references with Tell (see Ans. 18-
20).

CONCLUSION
On the record before us, we conclude that, because Tell teaches all the
claim limitations, the Examiner has not erred in rejecting claim 1 as being
anticipated by Tell. Therefore, we sustain the rejection of claim 1 and of
claims 2-20 falling therewith.

Appeal 2010-006301
Application 11/095,770

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DECISION
The Examiner’s decision rejecting claims 1-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD