Ex Parte Mitsugi et al

Patent Trial and Appeal Board

Jul 20, 2016

13543950 (P.T.A.B. Jul. 20, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/543,950 07/09/2012
124677 7590 07/22/2016
Russell Ng PLLC (IBM AUS)
8729 Shoal Creek Blvd., Suite 100
Austin, TX 78757
FIRST NAMED INVENTOR
Masanori Mitsugi
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
JP920110059US1 4717
EXAMINER
TSANG, KENNETH
ART UNIT PAPER NUMBER
2137
NOTIFICATION DATE DELIVERY MODE
07/22/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
s tephanie@russellnglaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MASANORI MITSUGI and HIROYUKI TANAKA
Appeal2015-003671
Application 13/543,950
Technology Center 2100
Before THU A. DANG, KRISTEN L. DROESCH, and
NORMAN H. BEAMER, Administrative Patent Judges.
DANG, Administrative Patent Judge.
DECISION ON APPEAL
I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 4--17. Claims 1-3 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.
A. INVENTION
According to Appellants, the invention relates to accessing
"hypervisor-controlled virtual machines in general, and in particular to a
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Application 13/543,950
method and apparatus for performing mapping within a data processing
system having multiple virtual machines" (Spec. 1, 11. 16-18).
B. REPRESENTATIVE CLAIM
Claim 4 is exemplary:
4. A non-transitory computer readable device having a
computer program product for performing mapping within a data
processing system having virtual machines, said computer
readable device comprising:
program code for, in response to a demand to access
a real memory address by a virtual machine having an
associated logical address:
sending a first instruction from said virtual machine
to a central processing unit of a data processing
system via a hypervisor, wherein said first
instruction requests said logical address to be
translated by said central processing unit to
encrypted real address information; and
sending a second instruction from said virtual
machine to an accelerator, in response to a receipt
of said encrypted real address information from said
central processing unit by said vi 1 iual machine,
wherein said second instruction requests said
accelerator to decrypt said encrypted real address
information into a set of real address information in
order to avoid using said hypervisor to perform
mapping; and
program code for accessing a memory device within said
data processing system by said accelerator using a real address
included within said set of real address information.
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C. PRIOR ART REFERENCES AND REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Bisbee
Yamazaki
Glew
US 2002/0184217 Al
US 2010/0281257 Al
US 2013/0031364 Al
Dec. 5, 2002
Nov. 4, 2010
Jan. 31, 2013
Claims 4--6 stand provisionally rejected on the ground of nonstatutory
obviousness-type double patenting as being unpatentable over claims 1-3 of
copending Application No. 13/780,335 (Fin. Act. 19-20).
Claims 4, 7, and 10-17 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the teachings of Appellants' Admitted Prior Art (AAPA)
and Glew.
Claims 5 and 8 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the teachings of AAP A, Glew, and Yamazaki.
Claims 6 and 9 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the teachings of AAP A, Glew, and Bisbee.
II. ISSUES
The principal issues before us are whether the Examiner erred in
finding that the combination of AAP A and Glew teaches or would have
suggested sending "a first instruction from said virtual machine to a central
processing unit of a data processing system via a hypervisor" that "requests
said logical address to be translated by said central processing unit to
encrypted real address information" and sending "a second instruction from
said virtual machine to an accelerator" that "requests said accelerator to
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Application 13/543,950
decrypt ... in order to avoid using said hypervisor to perform mapping"
(claim 4, emphases added).
III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Appellants' Admitted Prior Art (AAP A)
1. Appellants admit as prior art that when a guest partition needs to
access its memory space, a "hypervisor" converts the logical address of the
memory space to a physical address of a memory device by way of a
conversion table (Spec. 1, 11. 29--31 ).
2. Appellants also admit it is known that, to increase the processing
speed, processors within a data processing system offloads those tasks to a
hardware "accelerator" within the data processing system (Spec. 2, 11. 4---6).
Glew
3. Glew discloses encrypting and decrypting address and data
information to enable security (i-f 344).
IV. ANALYSIS
Provisional Double Patenting
The Examiner provisionally rejects claims 4---6 on the ground of
nonstatutory obviousness-type double patenting as being unpatentable over
claims 1-3 of copending Application No. 13/780,335 (Fin. Act. 19--20).
However, Appellants do not contest the rejection. Arguments not made are
considered waived. 1 See 37 C.F.R. § 41.37(c)(l)(iv). Therefore, we pro
1 See Hyatt v. Dudas, 551F.3d1307, 1314 (Fed. Cir. 2008) ("When the
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Application 13/543,950
forma sustain the Examiner's non-provisional obviousness-type double
patenting rejection of claims 4---6.
35 US.C. § 103(a)
Appellants contend that AAPA's "physical address is not the same as
encrypted real address information" (App. Br. 5). Appellants further
contend "the translation method disclosed by the AAP A is different from the
claimed translation method" since the hypervisor, and not the claimed
central processing unit as the Examiner finds, converts the logical address
(App. Br. 6).
Appellants then contend "paragraph 0344 of Glew does not disclose
how 'to avoid using said hypervisor to perform a mapping function,' as
claimed" (App. Br. 7). According to Appellants, although the Examiner
finds that "the AAP A provides the framework for allowing a virtual machine
to pass address information to a hardware accelerator," "[t]he Examiner has
clearly misinterpreted the teachings of AAP A" wherein in AAP A, "[a]
hypervisor typically performs any required mapping" (id.)
We have considered all of Appellants' arguments and evidence
presented. However, we disagree with Appellants' contentions regarding the
Examiner's rejections of the claims. We agree with the Examiner's findings,
and are unpersuaded of error with the Examiner's conclusion that the
claimed subject matter would have been obvious over the combined
teachings.
[A ]ppellant[ s] fail[] to contest a ground of rejection to the Board, section
1.192(c)(7) [(now section 41.37(c)(l)(vii))] imposes no burden on the Board
to consider the merits of that ground of rejection .... [T]he Board may treat
any argument with respect to that ground of rejection as waived.").
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As an initial matter, we note Appellants' contentions are directed to
what AAPA or Glew does not disclose separately (App. Br. 5-7). However,
the test for obviousness is what the combination of AAP A and Glew teaches
or would have suggested to one of ordinary skill in the art. See In re Merck
& Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Although Appellants contend that AAPA's "physical address is not
the same as encrypted real address information" (App. Br. 5), as the
Examiner points out, "[i]n the Final Office Action, AAPA alone was not
cited to teach that the translated address information is encrypted real
address information" (Ans. 3). Rather, the Examiner finds "when modified
by the address encryption-decryption scheme of Glew," the guest partition of
AAP A "would request encrypted real address information" for the benefit of
"enhanced memory access protection or security" (Ans. 3). We agree with
the Examiner's findings.
In particular, the Examiner finds, and we agree, according to AAP A, a
"hypervisor" converts "the logical address of the memory space to a physical
address of a memory device" (Ans. 3--4; FF 1 ), wherein a "hypervisor is a
piece of software running on a CPU" and the CPU "controls the operations
of the system" (Ans. 4). Accordingly, although Appellants contend that
AAPA's hypervisor, and not the claimed central processing unit the
Examiner finds, converts the logical address (App. Br. 6), we find no error
with the Examiner's reliance on AAP A for teaching or at least suggesting
translating a logical address by a "central processing unit" (on which the
hypervisor software is run) to a real address information, as required by
claim 4.
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Furthermore, Glew further discloses encrypting and decrypting the
address for further security (FF 3). We agree with the Examiner's finding
"when modified by the address encryption-decryption scheme of Glew," the
guest partition of AAP A "would request encrypted real address information"
for the benefit of "enhanced memory access protection or security" (Ans. 3).
Thus, we find no error with the Examiner's reliance on the combination of
AAP A and Lew for teaching or suggesting translating a logical address to
"encrypted" real address information, as required by claim 4.
Although Appellants contend that "paragraph 0344 of Glew does not
disclose how 'to avoid using said hypervisor to perform a mapping
function,' as claimed" (App. Br. 7), as Appellants point out, the Examiner
relies on AAP A for providing "the framework for allowing a virtual machine
to pass address information to a hardware accelerator" (id.). In particular,
AAP A discloses it is known that, to increase the processing speed, tasks are
offloaded to an accelerator (FF 2). The Examiner finds, and we agree, the
accelerator disclosed by AAPA receives instructions and address
information, thus, in "the system of AAPA modified by Glew, the function
of decrypting the address can be offloaded to the hardware accelerator" to
"help improve CPU speed" (Ans. 6). Accordingly, we find no error with the
Examiner's reliance on AAPA (in view of Glew) for teaching or at least
suggesting offloading an instruction from a virtual machine to an
"accelerator" that "requests said accelerator to decrypt ... in order to avoid
using said hypervisor to perform mapping," as required by claim 4.
The Supreme Court holds that the conclusion of obviousness can be
based on the background knowledge possessed by a person having ordinary
skill in the art. KSR Int'! Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007).
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The skilled artisan is "[a] person of ordinary creativity, not an automaton."
Id. at 421. We agree with the Examiner that the combination of AAP A and
Glew would at least have suggested the contested limitations. That is, we
agree with the Examiner that Appellants' invention is simply a modification
of familiar prior art teachings (as taught or suggested by the cited references)
that would have realized a predictable result. See id.
Based on the record before us, Appellants have not shown the
Examiner erred in rejecting claim 4 and claims 7 and 10-17, not separately
argued and thus falling therewith (App. Br. 5) over AAP A and Glew.
Appellants do not provide separate arguments for dependent claims 5, 6, 8,
and 9, respectively depending from claims 4 and 7. Accordingly, we also
affirm the Examiner's rejection of claims 5 and 8 over AAP A, and Glew, in
further view of Yamazaki; and of claims 6 and 9 over AAP A, and Glew, in
further view of Bisbee.
We note that Appellants introduce new arguments in the Reply Brief
(Reply Br. 2-3). However, it is inappropriate for Appellants to discuss for
the first time in a Reply Brief matters that could have been raised in the
Appeal Brief. Because Appellants advance new arguments in the Reply
Brief without showing good cause, Appellants have waived such arguments.
See 37 C.F.R. § 41.41(b)(2).
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V. CONCLUSION AND DECISION
We affirm the Examiner's rejections of claims 4--17 under 35 U.S.C.
§ 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 3 7 C.F .R. § 1.13 6( a )(1 )(iv).
AFFIRMED
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