Ex Parte MITCHLER

Patent Trial and Appeal Board

Feb 21, 2019

15194803 (P.T.A.B. Feb. 21, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
15/194,803 06/28/2016 Dennis Wayne MITCHLER
134545 7590 02/25/2019
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (DW)
5005 E. McDowell Road, Maildrop A 700
Phoenix, AZ 85008
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
ONS02064US 3177
EXAMINER
LEE,SIUM
ART UNIT PAPER NUMBER
2632
NOTIFICATION DATE DELIVERY MODE
02/25/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@onsemi.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DENNIS WAYNE MITCHLER
Appeal2018-006952
Application 15/194, 803
Technology Center 2600
Before JOHNNY A. KUMAR, CARLL. SILVERMAN, and SCOTT E.
BAIN, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1, 3, 4, 13, and 23-25, and 30-33. We have jurisdiction
under 35 U.S.C. § 6(b).
We REVERSE.
Appeal2018-006952
Application 15/194,803
INVENTION
Claim 1 is illustrative and is reproduced below:
A system, comprising:
a receiver configured to receive wireless signals from an electronic device,
the receiver comprising:
receiver logic operable to receive an input signal at a source clock
frequency from the electronic device;
a phase detector coupled to the receiver logic and operable to:
receive a data sampling clock; and
compute an error signal indicating a difference between the data
sampling clock and the source clock; and
a first communication interface coupled to the phase detector and
operable to transmit the input signal; and
a signal processor (SP) coupled to the receiver and comprising:
a second communication interface operable to couple to the first
communication interface to communicatively couple the SP to the
receiver;
a digitally-controlled oscillator (DCO) coupled to the second
communication interface and operable to generate a system clock;
a clock divider coupled to the DCO and the phase detector and
operable to generate the data sampling clock based at least partially on
the system clock; and
digital signal processing logic coupled to the DCO and the
clock divider and operable to process the input signal at a frequency
specified by the data sampling clock.
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Appeal2018-006952
Application 15/194,803
REJECTIONS AT ISSUE 1
A. Claims 1, 3, 4, 13, and 23-33 are rejected under 35 U.S.C. § 112, first
paragraph as failing to comply with the written description
requirement. (Final Act. 3-4; Ans. 2.)
B. Claims 26-28 are rejected under 35 U.S.C. § 103 as being
unpatentable over Lu (US 2006/0078079 Al) in view of Xiu (US
8,929,467 B 1 ).
C. Claim 29 is rejected under 35 U.S.C. § 103 as being unpatentable over
Lu, Xiu, and Kim (US 2015/0214960 Al).
ANALYSIS 2
Did the Examiner err in rejecting claims I, 3, 4, 13, and 23-25,
and 30-33under 35 USC § 112, first paragraph, as failing to
comply with the written description requirement?
Appellant contends:
At page 6, lines 21-22, Appellant's specification states that
"Alternatively, parallel interfaces may be used." Additionally,
1 On page 2 of the Final Action, under Response to Arguments, the
Examiner states "Applicant's arguments, see page 6-9, filed on 10/16/2017,
with respect to the rejections of claims 1, 3-4 and 16-22 under 35 U.S.C. §
I03(a) have been fully considered and are persuasive. Therefore, the
rejection has been withdrawn. However, upon further consideration, a new
ground(s) of rejection is made in view of Lu (US 2006/0078079 Al)."
( emphasis added). We note that this rejection is not described under "Claim
Rejections - 35 USC 103" in the Final Action (pages 5-8). Also in the
Grounds of Rejection section of the Answer the Examiner did not repeat the
§ 103 rejection of claims 1, 3, 4, and 16-22. We find that the Examiner's
statement about the new ground of rejection was an inadvertent and harmless
error.
2 Appellant has cancelled claims 26-29 (Amendment dated February 7,
2018). The Examiner has withdrawn the 103 rejections. Ans. 2.
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Appeal2018-006952
Application 15/194,803
as previously established in the Appeal Brief, Appellant's
specification teaches that the disclosed "receiver 200 and DSP 202
may communicate with each other in various ways, and in at least
some embodiments, such communication includes the use of a serial
link via serial interfaces 306 and 308." Specification at p. 6, 11. 16-19.
Furthermore, Appellant's specification states that "the receiver 200
receives wireless signals (e.g., audio signals) from the electronic
device 102 (Figure 1) via the antenna 208[]" and that "DSP 202
receives the signals from the receiver 200 and processes them for
output via the output 212." Specification at p. 5, 11. 11-16. Thus, the
specification clearly and unambiguously states that the receiver 200
and DSP 202 communicate via an interface such as a serial interface,
and that the receiver 200 receives wireless signals and provides them
to the DSP 202 for processing and output.
(Reply Br. 2.)
Sufficiency of written description requires that the original disclosure
reasonably convey to a person having ordinary skill in the art that the
inventor had possession of the claimed subject matter at the time of filing.
The exact level of detail required depends upon "the nature and scope of the
claims and on the complexity and predictability of the relevant technology."
Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010)
(en bane).
The Examiner finds "[ s ]ince the specification does not teach the serial
interface transmit the input signal received by the receiver logic, the
examiner interpret the limitation as a new matter." (Final Act. 3, 4)
We disagree with the Examiner's findings and agree with Appellant's
contentions. We disagree with the Examiner because we find a person of
ordinary skill in the art would recognize that Appellant's disclosure provides
support for the recited "receiver logic operable to receive an input signal at a
source clock frequency from the electronic device; ... a first communication
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Appeal2018-006952
Application 15/194,803
interface coupled to the phase detector and operable to transmit the input
signal" as recited in claim 1 and as commensurately recited in independent
claims 30. In particular, we find Appellant's disclosure at Specification
pages 5, lines 11-16, and page 6, lines 8-25 provides adequate disclosure.
We agree with Appellant's contentions that the Specification reasonably
conveys possession of the claimed subject matter.
Accordingly, Appellant has provided sufficient evidence or argument
to persuade us of at least one reversible error in the Examiner's written
description rejection of claim 1. Therefore, for essentially the same reasons
argued by Appellant cited above, we reverse the Examiner's rejection of
independent claim 1, and also reverse the rejection of independent claim 30,
which recite the disputed limitation in commensurate form. For the same
reasons, we also reverse the rejections under 35 U.S.C. § 112, first
paragraph, written description, of all dependent claims: 3, 4, 13, 23-25, and
31-33.
DECISION
The Examiner's decision to reject claims 1, 3, 4, 13, 23-25, and 30-
33 under 35 U.S.C. §112, first paragraph for lack of written description is
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
REVERSED
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