Ex Parte Min et al

Patent Trial and Appeal Board

Dec 27, 2016

12648111 (P.T.A.B. Dec. 27, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/648,111 12/28/2009 Woongki Min 12972-8052 3171
757 7590
BGL
P.O. BOX 10395
CHICAGO, IL 60610
12/27/2016 EXAMINER
YANG, KWANG-SU
ART UNIT PAPER NUMBER
2691
MAIL DATE DELIVERY MODE
12/27/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WOONGKI MIN and JUYOUNG LEE1
Appeal 2015-003555
Application 12/648,111
Technology Center 2600
Before JUSTIN BUSCH, DANIEL N. FISHMAN, and
JAMES W. DEJMEK, Administrative Patent Judges.
FISHMAN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1—3 and 5—8.2 Claim 4 has been canceled. App. Br. 12. We heard
oral argument Friday, December 9, 2016. A transcript of that hearing will
be filed in due course. We have jurisdiction over the pending claims under
35 U.S.C. § 6(b).
We affirm.
1 Appellants identify LG Display Co., Ltd. as the real party in interest.
Appeal Brief 2.
2 In this Decision, we refer to Appellants’ Appeal Brief (“App. Br.,” filed
August 4, 2014); Appellants’ Reply Brief (“Reply Br.,” filed February 18,
2015); the Final Office Action (“Final Act.,” mailed December 26, 2013);
the Examiner’s Answer (“Ans.,” mailed on December 3, 2014); and the
original Specification (“Spec.,” filed December 28, 2009).
Appeal 2015-003555
Application 12/648,111
THE INVENTION
Appellants’ invention is generally directed to a liquid crystal display.
Spec. 12. More specifically, the invention is directed to a liquid crystal
display having a timing controller that does not divide red, green, and blue
video data into odd and even data and, thereby, reduces the number of data
lines required in the display board—thus reducing the size of the printed
circuit board for the liquid crystal display. See Spec. H 41, 42.
Independent claim 1, reproduced below, is illustrative with a disputed
limitation in italics:
1. A liquid crystal display comprising:
a timing controller that outputs a pair of R digital video
data, a pair of G digital video data, a pair of B digital video
data, and a pair of clocks without dividing each of the R, G, and
B digital video data into an odd digital video data and an even
digital video data, wherein the pair of each of R, G, and B
digital video data includes positive data and negative data, and
wherein the pair of clocks includes a positive clock and a
negative clock;
a plurality of source driver integrated circuits (ICs), each
of which receives the pair of each of R, G, and B digital video
data and the pair of clocks from the timing controller to
generate a positive analog data voltage and a negative analog
data voltage and supplies the positive and negative analog data
voltages to data lines of a liquid crystal display panel; and
a source printed circuit board (PCB) having three pairs of
data bus lines and a pair of clock lines, the three pairs of data
bus lines and the pair of clock lines connecting output terminals
of the timing controller to input terminals of the plurality of
source driver ICs,
wherein the R, G, and B digital video data are transmitted
to the plurality of source driver integrated circuits through only
the three pairs of data bus lines, and
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Appeal 2015-003555
Application 12/648,111
wherein a transfer frequency of the pair of clocks output
from the timing controller is four times greater than an input
frequency of a clock signal input to the timing controller.
THE REJECTIONS
Claims 1—3 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Song et al. (US 2008/0225036 Al; pub. Sept. 18, 2008)
(“Song”) and Kim et al. (US 2009/0079716 Al; pub. Mar. 26, 2009)
(”Kim”). Final Act. 2—6.
Claims 5—8 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Song, Kim, Tashiro (US 2006/0256099 Al; pub. Nov. 16,
2006), and Tsao et al. (US 2009/0274241 Al; pub. Nov. 5, 2009) (“Tsao”).
Final Act. 6—10.
ANALYSIS
Only those arguments actually made by Appellants have been
considered in this Decision. Arguments that Appellants did not make in the
Briefs are waived. See 37 C.F.R. § 41.37(c)(l)(iv).
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner erred. App. Br. 5—9; Reply Br. 2—A. We are
not persuaded by Appellants’ contentions of Examiner error. Accordingly,
we adopt as our own the Examiner’s findings and reasons set forth in the
Final Action and the Answer. We highlight and address specific arguments
and findings for emphasis as follows.
The Examiner finds Song discloses all features of claim 1 (Final Act.
2—4) except “without dividing each of the R, G, and B digital video data into
an odd digital data and an even digital data, wherein the R, G, and B digital
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Appeal 2015-003555
Application 12/648,111
video data transmitted to the plurality of source driver ICs through only
three pairs of data bus lines” {id. at 4). The Examiner finds Kim discloses
this feature absent from Song and articulates a reason for combining the
references based on rational underpinnings. Id. at 4—6.
In particular, the Examiner finds Song discloses the disputed
limitation citing Song paragraph 78 and Figures 9 and 10. Final Act. 4.
Figures 9 and 10 of Song are reproduced below.
Fig. 9
31
RGB(f)
63
fj RGBodd,
RG Seven
Song’s Figure 9 shows timing control 31 comprising two port expansion part
34 and data modulator 35. Song 175. Timing controller 31 receives RGB
signals having a frequency “f ’ and generates RGBodd and RGBeven signals
having a frequency “2f.” See id. 176.
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Appeal 2015-003555
Application 12/648,111
Fig. 10
Bbit Data 1001111010111001
Data CLK
mini LVDS C
mini LVDS RGBT
reset
i_n
t
start
LTU
Song’s Figure 10 shows a relationship between Data CLK and mini LVDS
CLK where Data CLK “represents a data clock generated from the main
system board, and mini LVDS CLK represents a clock which is generated
from the data modulator 35.” Id. 178. Thus, according to Song’s paragraph
78, mini LVDS CLK has a frequency four times that of Data CLK. Relying
on this disclosure of Song, the Examiner finds, “[t]he frequency of mini
Data CLK is a clock signal input to the timing controller and mini LVDS
CLK is a clock signal output from the timing controller. The frequency of
mini LVDS CLK is four times greater than that of Data CLK.” Final Act. 4
(citing Song 178, Figs. 9-10).
Regarding Song’s paragraph 78 and Figure 10, Appellants argue “the
cited portion is obviously mistyped of the description ‘Data CLK represents
a data clock generated from the two port expansion part 34 of the timing
controller 31...’” App. Br. 7 (emphases omitted). Appellants provide
substantial analysis of other portions of Song that support the contention that
paragraph 78 is in error. Id. at 7—9. In particular, Appellants argue Song’s
Figure 9 would be understood by an ordinarily-skilled artisan to include an
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Appeal 2015-003555
Application 12/648,111
input clock to sample the RGB data at a clock frequency of “f ’ as input to
timing controller 31 and a clock frequency of “2f” as a generated output of
timing controller 31. App. Br. 6. We agree. Furthermore, Figure 9 also
makes clear that the input clock with frequency “f ’ is divided by 2 by
operation of two port expansion part 34 within timing controller 31. That
generated clock signal having a frequency “f/2” is then applied to data
modulator 35 within timing controller 31, which, in turn, generates an output
clock signal having a frequency “2f.” Thus, data modulator 35 receives an
input clock and generates an output clock having a frequency four times
greater than its input. See id. at 7—8; see also Reply Br. 2—\.
Although we agree with Appellants that Song appears to include a
typographic error, we are not persuaded the Examiner erred by finding the
proposed combination renders claim 1 obvious. “Even if a reference
discloses an inoperative device, it is prior art for all that it teaches.”
Beckman Instruments, Inc. v. LKB Produkter AB, 892 F.2d 1547, 1551 (Fed.
Cir. 1989). “While a reference must enable someone to practice the
invention in order to anticipate under § 102(b), a non-enabling reference
may qualify as prior art for the purpose of determining obviousness under
§ 103.” Symbol Techs., Inc. v. Opticon, Inc., 935 F.2d 1569, 1578 (Fed. Cir.
1991). Thus, even granting that Song includes a typographic error, we
conclude Song at least suggests to the ordinarily skilled artisan that a timing
controller may generate an output clock that is four times the frequency of
an input clock applied to the timing controller.
In view of the above discussion, we are not persuaded the Examiner
erred in rejecting independent claim 1. For the same reasons, we are not
persuaded the Examiner erred in rejecting claims 2, 3, and 5—8, not argued
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separately. App. Br. 9. Thus, we sustain the Examiner’s rejections of
claims 1—3 and 5—8.
DECISION
We affirm the Examiner’s decision to reject claims 1—3 and 5—8.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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