Ex Parte Milliken

Board of Patent Appeals and Interferences

Jul 31, 2008

10166547 (B.P.A.I. Jul. 31, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte WALTER CLARK MILLIKEN
____________

Appeal 2008-0702
Application 10/166,5471
Technology Center 2100
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Decided: July 31, 2008
____________

Before LANCE LEONARD BARRY, JEAN R. HOMERE, and
JAY P. LUCAS, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1 through 37 and 54 through 58. Claims 38 through 53

1 Filed on Jun. 10, 2002. The real parties in interest are Verizon Corporate
Services Group Inc., and BBNT Solutions LLC.
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have been withdrawn. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm-in part.

The Invention
Appellant invented a method and system for providing parallel packet
high performance cryptography in a network device to ensure that outgoing
packets are output in the same order in which they were received. (Spec. 8.)
As depicted in Figure 5, upon receiving each incoming packet, a scheduler
(530) assigns the packet to a corresponding one of a plurality of
cryptographic sub units (510) having an input buffer (520) with the least
amount of data stored therein. (Spec. 12.) After performing the necessary
cryptographic operation on the packets, the cryptographic sub units transfer
the transformed blocks from the assigned sub units to a re-assembler (540),
which subsequently re-assembles the packets, and outputs them in the same
order in which they arrived at the scheduler. (Spec. 13.)

An understanding of the invention can be derived from exemplary
independent claims 1 and 20, which read as follows:
1. A cryptographic system, comprising:

a plurality of input buffers configured to temporarily store a plurality
of packets, each of the packets including one or more data blocks;

a plurality of cryptographic sub-units associated with the input
buffers, each of the sub- units being configured to perform a cryptographic
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operation on the data blocks from the associated input buffer to form
transformed blocks;

a scheduler configured to assign each of the packets to one of the sub-
units, as an assigned sub-unit, based on an amount of data stored in the
associated input buffer; and

a reassembler configured to:

receive the transformed blocks from the assigned sub-units,

reassemble the packets from the transformed blocks to form
reassembled packets, and

output the reassembled packets in a same order in which the
packets arrived at the scheduler.

20. A cryptographic system, comprising:

a plurality of cryptographic sub-units, each of the sub-units being
configured to perform a cryptographic operation on data blocks associated
with a plurality of packets to form transformed blocks;

a scheduler configured to:

receive the packets,

identify the sub-units, as identified sub-units, that would output
the packets the soonest, and

assign the packets to the identified sub-units; and

a reassembler configured to:

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receive the transformed blocks from the identified sub-units,

reassemble the packets from the transformed blocks to form
reassembled packets, and

output the reassembled packets in a same order in which the
packets were received by the scheduler.

In rejecting the claims on appeal, the Examiner relied upon the
following prior art:
Krishna US 2003/0014627A1 Jan. 16, 2003
(filed Aug. 12, 2002)

The Examiner rejected the claims on appeal as follows:
1. Claims 1, 2, 4 through 12, 14 through 23, 25 through 37, and 54 through
58 stand rejected under 35 U.S.C. § 102(e) as being anticipated by Krishna.

2. Claims 3, 13, and 24 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Krishna.

FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.
Krishna
1. Krishna discloses an accelerated cryptography chip that
processes packets in parallel to efficiently encrypt/decrypt the packets. (P.
1, para. [0010].)
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2. As depicted in Figure 3, the accelerated cryptography chip
(300) includes a plurality of cryptography engines (316) configured in
parallel. Each engine has an input buffer (312) associated therewith for
storing packet information to be processed by the corresponding engine. (P.
5, para. [0053].)
3. The chip further includes a packet distributor (206) that assigns
each incoming packet to the next free crypto engine in order to output the
packets in the same order in which they arrived at the distributor. (PP. 3-4,
para. [0041].)

PRINCIPLES OF LAW
ANTICIPATION
It is axiomatic that anticipation of a claim under § 102 can be found
only if the prior art reference discloses every element of the claim. See In re
King, 801 F.2d 1324, 1326 (Fed. Cir. 1986) and Lindemann
Maschinenfabrik GMBH v. American Hoist & Derrick Co., 730 F.2d 1452,
1458 (Fed. Cir. 1984).

In rejecting claims under 35 U.S.C. § 102, a single prior art reference
that discloses, either expressly or inherently, each limitation of a claim
invalidates that claim by anticipation. Perricone v. Medicis Pharmaceutical
Corp., 432 F.3d 1368, 1375-76 (Fed. Cir. 2005), citing Minn. Mining & Mfg.
Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed.
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Cir. 1992). Anticipation of a patent claim requires a finding that the claim at
issue “reads on” a prior art reference. Atlas Powder Co. v. IRECO, Inc.,
190 F.3d 1342, 1346 (Fed Cir. 1999) (“In other words, if granting patent
protection on the disputed claim would allow the patentee to exclude the
public from practicing the prior art, then that claim is anticipated, regardless
of whether it also covers subject matter not in the prior art.”) (internal
citations omitted).

OBVIOUSNESS
Appellant has the burden on appeal to the Board to demonstrate error
in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir.
2006) (“On appeal to the Board, an applicant can overcome a rejection
[under § 103] by showing insufficient evidence of prima facie obviousness
or by rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir.
1998)).
The Supreme Court in Graham v. John Deere Co., 383 U.S. 1, 17-18
(1966), stated that the following factual inquiries underpin any
determination of obviousness:
Under § 103, [1] the scope and content of the prior art are to be
determined; [2] differences between the prior art and the claims
at issue are to be ascertained; and [3] the level of ordinary skill
in the pertinent art resolved. Against this background, the
obviousness or nonobviousness of the subject matter is
determined. Such (4) secondary considerations as commercial
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success, long felt but unsolved needs, failure of others, etc.,
might be utilized to give light to the circumstances surrounding
the origin of the subject matter sought to be patented. As
indicia of obviousness or nonobviousness, these inquiries may
have relevancy.
Where the claimed subject matter involves more than the simple
substitution of one known element for another or the mere application of a
known technique to a piece of prior art ready for the improvement, a holding
of obviousness must be based on “an apparent reason to combine the known
elements in the fashion claimed.” KSR Int’l v. Teleflex, Inc., 127 S. Ct.
1727, 1740-41 (2007). That is, “there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness.” Id., 127 S. Ct. at 1741, (quoting In re Kahn, 441 F.3d 977,
988 (Fed. Cir. 2006)). Such reasoning can be based on interrelated teachings
of multiple patents, the effects of demands known to the design community
or present in the marketplace, and the background knowledge possessed by a
person having ordinary skill in the art. KSR, 127 S. Ct. at 1740-41.

ANALYSIS
Claims 1-19, and 54-56
Independent claims 1, 10, 11, and 54 recite in relevant part a
scheduler configured to assign each of the packets to one of the sub units
based on an amount of data stored in the associated input buffer. (Claims
Appendix.) Appellant argues that Krishna does not teach that limitation.
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Particularly, Appellant submits that Krishna discloses a distributor that
assigns an incoming packet to a crypto engine based on its availability, as
opposed to the amount of data its buffer contains. (App. Br. 18-20, Reply
Br. 2-3.) The Examiner, in response, finds that Krishna’s disclosure of
assigning an incoming packet to the next free crypto engine implies that its
corresponding buffer is empty, and therefore contains the least amount of
data. The Examiner consequently concludes that Krishna teaches selecting
the crypto engine based on the amount of data stored in its associated buffer.
(Ans. 7-9.)
Therefore, the first issue before us is whether one of ordinary skill in
the art would find that Krishna’s assignment of each incoming packet to the
next free crypto engine in a round robin fashion teaches assigning the packet
to the engine based on the amount of data contained in the input buffer of the
crypto engine, as claimed. We answer this inquiry in the negative.
As detailed in the Findings of Facts section above, Krishna discloses
an accelerated cryptography chip system having a plurality of parallel
engines for effectively processing incoming packets. (FF. 1.) Particularly,
Krishna discloses a distributor that assigns each incoming packet to the next
free crypto engine. (FF. 3.) One of ordinary skill in the art would readily
recognize, as correctly pointed out by Appellant, that the distributor assigns
the incoming packet to the crypto engine based on its availability in the
crypto engine pool. The ordinarily skilled artisan would appreciate that
selecting the next free engine in a round robin fashion purports to selecting
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from the engine pool the next engine, which is not processing any packet at
the time of distributor’s assignment of the packet. We do not agree with the
Examiner’s finding that the free engine implies an engine having an empty
input buffer corresponding thereto. The ordinarily skilled artisan would
recognize that at the time of the distributor’s packet assignment, although an
engine may not be processing a packet (i.e., free), its corresponding buffer
may be temporarily storing a packet, which has yet to be transferred to the
engine for processing. In this particular case, the input buffer is clearly not
empty. Consequently, we cannot support the Examiner’s finding of
inherency. It follows that Appellant has shown that the Examiner erred in
finding that Krishna anticipates independent claims 1, 10, 11, and 54.
Because dependent claims 2-9, 12-19, 55, and 56 incorporate the
limitations their respective base claims by dependency, it follows for the
aforementioned reasons that Appellant has shown that the Examiner erred in
finding that Krishna anticipates or renders those claims unpatentable.

Claims 20-37, 57, and 58
Independent claim 20 recites in relevant part a scheduler configured to
identify subunits that would output the packets the soonest. (Claim
Appendix.) Appellant argues that Krishna does not teach these limitations.
Particularly, Appellant submits that Krishna discloses a distributor
that assigns an incoming packet to the next free crypto engine, but not to an
engine that would output the packets the soonest. (App. Br. 20-21, Reply
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Br. 3-4.) The Examiner, in response, finds that Krishna’s disclosure of
assigning an incoming packet to the next free crypto engine would output
packets the soonest since they are processed in parallel in the same round
robin order in which they are input. (Ans. 10.)
Therefore, another issue before us is whether one of ordinary skill in
the art would find that Krishna’s assignment of each incoming packet to the
next free crypto engine in a round robin fashion teaches identifying subunits
that would output the packets the soonest, as claimed. We answer this
inquiry in the affirmative.
As set forth in the Findings of Fact, Krishna discloses a method and
system for accelerating the processing of packets as a way to efficiently
output the packets. (FF. 1.) Particularly, Krishna discloses assigning the
packets to the next free crypto engines in a round robin fashion, and
processing the packets in parallel in order to output them in the same order
in which they were assigned. (FF. 2-3.) One of ordinary skill would readily
recognize that Krishna’s disclosure of assigning the packets to free crypto
engines in a round robin fashion for parallel processing minimizes any delay
in processing the packets to expeditiously output them in the same order in
which they were processed. The ordinarily skilled artisan would thus
appreciate that such an approach of efficiently processing would result in
outputting the packets the soonest. It follows that Appellant has not shown
that the Examiner erred in finding that Krishna anticipates independent
claim 20.
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Appellant did not provide separate arguments with respect to the
rejection of claims 20-37, 57, and 58. Therefore, we select independent
claim 20 as being representative of the cited claims. Consequently, these
dependent claims fall together with representative claim 20. 37 C.F.R.
§ 41.37(c)(1)(vii).

CONCLUSION OF LAW
A. Appellant has shown that the Examiner erred in:
1. finding Krishna anticipates claims 1, 2, 4 through 12, 14 through 19,
and 54 through 56 under 35 U.S.C. § 102(e).
2. concluding that Krishna renders claims 3, and 13 unpatentable under
35 U.S.C. § 103(a).
B. Appellant has not shown that the Examiner erred in:
1. finding that Krishna anticipates claims 20 through 23, 25 through 37,
57, and 58 under 35 U.S.C. § 102(e).
2. concluding that Krishna renders claim 24 unpatentable under 35 U.S.C.
§ 103(a).

DECISION
We reverse the Examiner’s decision rejecting claims 1 through 19,
and 54 through 56. However, we affirm the Examiner’s decision rejecting
claims 20 through 37, 57, and 58.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

rwk

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