Ex Parte Milgrew et alDownload PDFPatent Trial and Appeal BoardJan 23, 201813607128 (P.T.A.B. Jan. 23, 2018) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/607,128 09/07/2012 Mark Milgrew LT00326.21 CONI 1484 52059 7590 01/25/2018 LIFE TECHNOLOGIES CORPORATION Attn: IP Department 5823 Newton Drive Carlsbad, CA 92008 EXAMINER CROW, ROBERT THOMAS ART UNIT PAPER NUMBER 1634 NOTIFICATION DATE DELIVERY MODE 01/25/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): LSGDocketing@thermofisher.com pair_thermofisher @ firsttofile. com LifetechDocket @ system.foundationip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MARK MILGREW, JAMES BUSTILLO, and TODD REARICK1 Appeal 2017-003762 Application 13/607,128 Technology Center 1600 Before DEMETRA J. MILLS, B. WILLIAM BAUMEISTER, and DEVON ZASTROW NEWMAN, Administrative Patent Judges. MILLS, Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35 U.S.C. § 134. The Examiner has rejected the claims for lack of written description and obviousness. We have jurisdiction under 35 U.S.C. § 6(b). We reverse the lack of written description and obviousness rejections in favor of a New Ground of Rejection of the claims for obviousness. 1 The real party in interest is the Assignee, Life Technologies Corporation. App. Br. 4. Appeal 2017-003762 Application 13/607,128 NATURE OF THE INVENTION According to the Specification paragraph 3, “[t]he present disclosure is directed generally to inventive methods and apparatus relating to detection and measurement of one or more analytes including analytes associated with or resulting from a nucleic acid synthesis reaction.” Also provided are methods for maintaining or increasing signal (and thus signal-to-noise ratio) when using very large chemFET arrays [chemically sensitive field effect transistor], and in particular when increasing the density of a chemFET array (and concomitantly decreasing the area of any single chemFET within the array). It has been found that as chemFET area decreases in order to accommodate an ever increasing number of sensors on a given array, the signal that can be obtained from a single chemFET may in some instances decrease. The invention provides in some aspects and embodiments methods for overcoming this limitation. Spec. ^ 39. “To reduce possible gate oxide degradation during plasma processing (e.g., plasma etch, sputtering, PECVD [plasma enhanced chemical vapor deposition], etc.), a well diode and/or a substrate diode may be employed, as illustrated in Figs. 15 75R-75T.” Id. ^[ 829. In addition, Various techniques employed in a conventional CMOS [complementary metal oxide semiconductor] fabrication process, as well as various post-fabrication processing steps (wafer handling, cleaning, dicing, packaging, etc.), may in some instances adversely affect performance of the resulting chemFET array. For example, ... one potential issue relates to trapped charge that may be induced in the gate oxide ... during etching of metals associated with the floating gate structure ..., and how such trapped charge may affect chemFET threshold voltage Vtit Another potential issue relates to the density/porosity of the chemFET passivation layer (e.g., see [ion- sensitive FET] ISFET passivation layer ...) resulting from low- temperature material deposition processes commonly employed in 2 Appeal 2017-003762 Application 13/607,128 aluminum metal-based CMOS fabrication. While such low- temperature processes generally provide an adequate passivation layer for conventional CMOS devices, they may result in a somewhat low- density and porous passivation layer which may be potentially problematic for chemFETs in contact with an analyte solution; in particular, a low-density porous passivation layer over time may absorb and become saturated with analytes or other substances in the solution, which may in turn cause an undesirable time-varying drift in the chemFETs threshold voltage Vth . This phenomenon may in turn impede accurate measurements of one or more particular analytes of interest. In view of the foregoing, other inventive embodiments disclosed herein relate to methods and apparatuses which mitigate potentially adverse effects on chemFET performance that may arise from various aspects of fabrication and post fabrication processing/handling of chemFET arrays. Id. 1J122. The method of the invention comprises depositing at least one additional passivation material on the chemically-sensitive passivation layer so as to reduce a porosity and/or increase a density of the passivation layer. Id. 1|135. The following claim is representative: 1. A method for manufacturing a chemically-sensitive field effect transistor, the method comprising: forming a gate dielectric on a semiconductor body; forming a floating gate structure, including a sensor plate, on the gate dielectric; forming a passivation layer over the sensor plate; and forming a diode to directly connect the floating gate structure to the semiconductor body; wherein forming the floating gate structure includes: forming a gate element on the gate dielectric, forming a plurality of patterned conductors in each member of a set of patterned conductor layers, the plurality of patterned conductors including the sensor plate, and connecting 3 Appeal 2017-003762 Application 13/607,128 the patterned conductors in the plurality together by interlayer connectors. Pending Grounds of Rejection 1. Claims 1 and 3-8 are rejected under 35 U.S.C. §112(a) or 35 U.S.C. §112 (pre-AIA), first paragraph, as failing to comply with the written description requirement, as new matter. 2. Claims 1, 3-9, and 11-14 are rejected under pre-AIA 35 U.S.C. §103 (a) as being unpatentable over Milgrew2 in view of Sawada3 and Hammond4. FINDINGS OF FACT The Examiner’s findings of fact are set forth in the Final Action at pages 4-10. 2 Mark J. Milgrew, Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge, 55 IEEE Transactions on Electron Devices 1074-1079 (2008). 3 US 2005/0062093 Al; published Mar. 24, 2005 4 Paul A. Hammond, et al., Design of a Single-Chip pH Sensor Using a Conventional 0.6-gm CMOS Process, 4 IEEE Sensors Journal 706712 (2004) 4 Appeal 2017-003762 Application 13/607,128 1. Figure 11A of the Specification is reproduced below. Figure 11 A shows the p substrate, highly doped p-type regions 156 and 158 ... in n-well 154 constitute the source (S) and drain (D) of the ISFET, between which lies a region 160 of the n-well in which the ISFETs p-channel is formed below the ISFETs polysilicon gate 164 and a gate oxide 165. ... Above the substrate, gate oxide, and polysilicon layers shown in Fig. 1 1A, a number of additional layers are provided to establish electrical connections to the various pixel components, including alternating metal layers and oxide layers through which conductive vias are formed. Pursuant to the example of a 4-Metal CMOS process, these layers are labeled in Fig. 11A as “Contact,” “Metal 1,” “Via 1,” “Metal 2,” “Via 2,” “Metal 3,” “Via 3,” and “Metal 4.”........With respect to the ISFET electrical connections, the topmost metal layer 304 corresponds to the ISFETs sensitive area 178 [sensing plate], above which is disposed an analyte-sensitive passivation layer 172. The topmost metal layer 304, together with the ISFET polysilicon gate 164 and the intervening conductors 306, 308, 312, 316, 320, 326 and 338, form the ISFETs “floating gate” structure 170, ... An electrical connection to the ISFETs drain is provided by the conductors 340, 5 Appeal 2017-003762 Application 13/607,128 328, 318, 314 and 310 coupled to the line 116 1. The ISFETs source is coupled to the shared drain of the 35 MOSFETs Q2 and Q3 via the conductors 334 and 336 and the conductor 324 .... The body connections 162 to the n-well 154 are electrically coupled to a metal conductor 322 around the perimeter of the pixel on the “Metal 1” layer via the conductors 330 and 332. Spec. 58-59, emphasis added. 2. Figure 75 S of the Specification is reproduced below. Figure 75S shows diode 75S 1 which connects the gate electrode of ISFET 75R3 to semiconductor substrate 75S2. Diode 75SI between the gate 75R1 of ISFET 75R3 and the substrate 75S2 limits the voltage that can build up on the gate relative to the substrate. Spec. ^831. 3. Sawada paragraph 28 discloses that, “the input gate, reset gate, and reset diode of each sensor element are formed commonly from the single input gate, single reset gate, and single reset diode extending to all elements.” 6 Appeal 2017-003762 Application 13/607,128 4. Figure 1 of Milgrew is reproduced below. Figure 1 of Milgrew shows a 3-D cross section through a pH-sensitive p-type ISFET with a floating gate electrode. P. 1075, left column. The oxynitride layer and nitride layer are above the ion sensing floating gate electrode. PRINCIPLES OF LAW As stated in TurboCare Div. of Demag Delaval Turbomachinery Corp. v. General Elec. Co., 264 F.3d 1111,1118 (Fed. Cir. 2001): The written description requirement and its corollary, the new matter prohibition of 35 U.S.C. § 132, both serve to ensure that the patent applicant was in full possession of the claimed subject matter on the application filing date. “When the applicant adds a claim or otherwise amends his specification after the original filing date . . ., the new claims or other added material must find support in the original specification.” The test for determining whether a Specification is sufficient to support a particular claim “is whether the disclosure of the application relied 7 Appeal 2017-003762 Application 13/607,128 upon ‘reasonably conveys to the artisan that the inventor had possession at that time of the later claimed subject matter.’” Ralston Purina Co. v. Far- Mar-Co, Inc., 772 F.2d 1570, 1575 (Fed. Cir. 1985) (quoting In re Kaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983)). Thus, “[i]t is not necessary that the application describe the claim limitations exactly, but only so clearly that persons of ordinary skill in the art will recognize from the disclosure that appellants invented processes including those limitations.” In re Wertheim, 541 F.2d 257, 262 (CCPA 1976) (citation omitted); see also Purdue Pharma L.P. v. Faulding, Inc., 230 F.3d 1320, 1323 (Fed. Cir. 2000) (“In order to satisfy the written description requirement, the disclosure as originally filed does not have to provide in haec verba support for the claimed subject matter at issue.”). In making our determination, we apply the preponderance of the evidence standard. See, e.g., Ethicon, Inc. v. Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988) (explaining the general evidentiary standard for proceedings before the Office). “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSRInFl Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Written Description - New Matter The Examiner finds that Claim 1, upon which claims 3-8 each depend, is amended to recite a diode that “directly” connects the floating gate structure to the semiconductor body. Applicant has provided no citation of support for this amendment. A review of the specification yields no teaching of a diode that “directly” connects the 8 Appeal 2017-003762 Application 13/607,128 floating gate structure to the semiconductor body. The amendment therefore constitutes new matter. Final Act. 3. Appellant contends that support for the diode directly connected to the floating gate is found in the Specification at Fig. 75S and that Fig. 75S clearly shows a diode directly connecting a floating gate structure to a semiconductor body. Fig. 75S and related description appearing at Paragraph [0842] show diode 75S1 which connects the gate electrode of ISFET 75R3 to semiconductor substrate 75S2. Applicant respectfully submits that one of ordinary skill in the art would readily conclude the inventor’s possession of the invention at the time of filing. App. Br. 9. The Examiner responds, explaining that Figure 75S is merely a diagram which shows diode 75SI adjacent substrate 75S2. Element 75R3 is also described as an ISFET. Paragraph 0842 states the diode 75S1 is “between the gate 75R1 of ISFET 75R3,) but the figure does not contain anything labeled “75R1” nor is there any simple teaching of any “direct” connection. It is also noted that element 75R2, which is specifically labeled as an ISFET in the diagram, has no description in paragraph 0842. Preceding paragraph 0841, which describes Figure 75R, also has an element numbered 75R2 and labeled “ISFET,” which is listed has having a gate. However, as with the example above, this example also lacks simple teaching of any “direct” connection. Ans. 4. ANALYSIS - New Matter We are not persuaded by the Examiner’s position that the amendment merits a written description/new matter rejection. Paragraph 830 of the Specification (corresponding to paragraph 842 of publication 9 Appeal 2017-003762 Application 13/607,128 US 2013/0017642 Al) indicates that the protection diodes of the invention may be either well diodes or substrate diodes. Thus, it would reasonably appear that the substrate diode connects the floating gate structure to the semiconductor substrate/body. Spec. ^ 803. In addition, original drawing 75S in US 2013/0017642 Al corresponds to Figure 75S in the present application. Appellants argue that, “Fig. 75S and related description appearing at Paragraph [0842] show diode 75S1 which connects the gate electrode of ISFET 75R3 to semiconductor substrate 75S2.” While the Fig. 75S description does not specifically use the phrase “directly connects,” one of ordinary skill in the art reading the circuitry diagram of Fig. 75S would understand that the circuitry directly connects a diode connecting the floating gate structure to the semiconductor body, as claimed. The rejection lacks a technical reason why one of ordinary skill in the art would not have read circuitry diagram 75S in this manner. The new matter rejection is reversed. Obviousness Rejection The Examiner finds that Milgrew teaches each element claimed, including diodes, but does not specifically teach the diode connected to the substrate. Final Act. 5. The Examiner finds that, “Sawada et al teach a method ISFETS, which are chemFETs (paragraph 0011) comprise first diode 2 connected to the substrate 1 and extend to all elements of the ISFET (paragraph 0028).” Id. The Examiner further finds that, “Sawada et al teach the diode 2 extends to all elements of the ISFET (paragraph 0028); thus, the diode is connected to the floating gate structure and the body, and thereby directly connects them.” Final Act. 6. The Examiner concludes that 10 Appeal 2017-003762 Application 13/607,128 The ordinary artisan would have been motivated to make the modification because said modification would have resulted in a method having the added advantage of allowing detection of nucleic acids as explicitly taught by Sawada et al (paragraph 0028). In addition, it would have been obvious to the ordinary artisan that the known technique of Sawada et al could have been applied to the method of Milgrew et al with predictable results because the known technique of Sawada et al predictably results in a useful FET structure for detection nucleic acids. Final Act. 7. Appellants argue that Sawada detects potential level changes of channel on the basis of the potential change of the surface of the detector. See Sawada, ^ [0001]. At Fig. 1, Sawada shows a sensor having semiconductor body 1, insulating film 5, input diode 2, floating diffusion section 3 and reset diode 4. The sensing section 9 of Sawada is positioned between input gate 6 and output gate 7. See Sawada [0073]—[0078]. Paragraph [0074] of Sawada provides: On the surface of the semiconductor substrate 1 between the input diode 2 and floating diffusion section 3, a conductive channel (n type inversion layer) is formed in relation to the gate structure described below, and hence, using the input diode 2 as the source and the floating diffusion section 3 as the drain, an FET type sensor is composed. Neither the input gate 6, nor the output gate 7 of Sawada is connecting a gate to the semiconductor substrate 1. In fact, the reference requires insulation film 5 to isolate gates 6 and 7 from the semiconductor body 1. Input diode 2 and reset diode 4 have no physical connection with gates 6 and 7 and are insulated therefrom. Clearly, Sawada does not disclose nor suggest the claimed recitations of “a diode to directly connect the floating gate structure to the semiconductor body” as recited in claim 1 or 11 Appeal 2017-003762 Application 13/607,128 “connecting the floating gate structure to the semiconductor body using a diode” as recited in independent claim 9. App. Br. 11-12. Appellants further argue that the “cited references fail to disclose or suggest a passivation layer formed over the sensor plate as claimed.” App. Br. 13. ANALYSIS - Obviousness We find that a preponderance of the evidence provided by the Examiner does not support a prima facie case of obviousness. Diode We do not agree that the Examiner has specifically shown that Sawada discloses “a diode to directly connect the floating gate structure to the semiconductor body,” as recited in claim 1. In particular, Sawada paragraph 51 states that This invention moreover presents a detecting method of base sequence by using an FET type sensor comprising an input diode section and a floating diffusion section consisting of a diffusion region reverse to the substrate in conductivity type, formed across a specified interval on semiconductor substrate, a sensing section having a gold film exposed on the surface and fixed by way of an insulation film, at a position on the substrate surface corresponding to the middle or initial end of a conductive channel to be formed on the substrate surface layer in the interval, wherein a potential well varying in the depth according to the ion density acting on the sensing section is formed in the middle of the conductive channel, and the electric charge according to the seepage amount from the potential well is measured in the floating diffusion section ... Emphasis added. 12 Appeal 2017-003762 Application 13/607,128 Sawada Fig. 1 is reproduced below. Fig. 1 Sawada Fig 1 shows a sectional view (A) and a schematic view (B) showing a basic potential state of FET type sensor in Embodiment 1 of the invention. Sawada]} 73. More particularly, Fig 1 shows On the surface of the semiconductor substrate 1 between the input diode 2 and floating diffusion section 3, a conductive channel (n type inversion layer) is formed in relation to the gate structure described below, and hence, using the input diode 2 as the source and the floating diffusion section 3 as the drain, an FET type sensor is composed. On the insulation film 5, an input gate 6 is formed at a position adjacent to the input diode 2 ... Sawada ]} 74. Appellants argue that, “Sawada does not disclose nor suggest the claimed recitations of “a diode to directly connect the floating gate structure to the semiconductor body.” App. Br. 11-12. The Examiner maintains that paragraph 28 of Sawada supports that the diode “directly connects] the floating gate structure to the semiconductor body.” 13 Appeal 2017-003762 Application 13/607,128 Paragraph 28 of Sawada states that “the input gate, reset gate, and reset diode of each sensor element are formed commonly from the single input gate, single reset gate, and single reset diode extending to all elements. We find that Appellant has the better argument. The Examiner has not established that Fig. 1 of Sawada clearly shows a diode directly connecting the floating gate structure to the semiconductor body, as claimed. We likewise do not find that the Examiner has provided a clear teaching in either Milgrew or Sawada of a diode directly connecting the floating gate structure to the semiconductor body, as claimed. For this reason, the obviousness rejection is reversed. NEW GROUND OF REJECTION Pursuant to our discretionary authority under 37 C.F.R. § 41.50(b), we enter a new ground of rejection for claim 1 under 35 U.S.C. § 103(a) as being unpatentable over Appellants’ admitted prior art in view of Gradenwitz (US 5,986,308; issued Nov. 16, 1999) or Bryant (US 6,249,028 Bl; issued June 19, 2001), either alone or in combination. Appellants acknowledge that every limitation of independent claim 1 was known, other than the method step of “forming a diode to directly connect the floating gate structure to the semiconductor body.” See Appellants’ Figure 1 (labeled as “Prior Art”); Spec. 4-10 (setting forth the associated discussion). Gradenwitz teaches forming an electrical contact 15 and a p-n diode 11-10 to directly connect track structure 9 of floating gate 8 to semiconductor body 11. Gradenwitz col. 5,11. 31^15; Fig. 8. Gradenwitz 14 Appeal 2017-003762 Application 13/607,128 explains that this direct electrical connection is performed for the following reason: In the manufacture of integrated circuits, damage to transistors caused by [electrostatic discharge] ESD is customarily precluded by connecting the gates of the transistors, in an early stage, to a protection diode. If, for example during plasma etching or reactive ion etching, an electric charge is stored on a floating gate, this charge can be removed via the diode before electric breakdown occurs. Gradenwitz Abstract; see also col. 1,11. 49-51 (“If, during the production process, electric charge is stored on the electrically floating gate, this charge can be removed via the diode before causing damage to the gate oxide”). Bryant similarly teaches a “floating gate protect diode structure” for silicon-on-insulator (SOI) devices that protects the gate oxide of an SOI metal-oxide-semiconductor field effect transistor (MOSFET). Bryant col. 2, 11. 60-63. This diode structure comprises N+ diffusion region 9 and p-well or body region of FET 7 (id. col. 4,11. 8-19), as well as local interconnect 5 formed on gate 3 and directly connecting the gate to the semiconductor body via the p-n diode (id. col. 5,11. 49-56). The protection diode “provides a conductive path from the gate of an SOI MOSFET to the body [and] protects the gate from charging, particularly charging during the manufacturing process. Id. col. 2,11. 63-67. It would have been obvious to one of ordinary skill in the art at the time of the invention to have modified the floating gate device depicted in Appellants’ Prior-Art Figure 1 so as to incorporate a diode to directly connect the floating gate structure to the semiconductor body, as taught by either one of Gradenwitz and Bryant, alone or in combination. One would have been motivated to incorporate such a protection-diode structure in 15 Appeal 2017-003762 Application 13/607,128 order to protect the prior-art floating gate from collecting a charge sufficient to cause breakdown of the underlying gate oxide, as taught by both Gradenwitz (col. 1,11. 49-51) and Bryant (col. 2,11. 63-67).5 Because the Patent Trial and Appeals Board is a review body, rather than a place of initial examination, we have not reviewed the remaining claims to the extent necessary to determine whether new grounds of rejection would be appropriate for any of these additional claims. We emphasize, though, that our decision to address only claim 1 does not mean the remaining claims are patentable. Rather, we leave it to the Examiner to determine the appropriateness of any further rejections based upon the prior art and rationales set forth above. 5 Upon any further prosecution, the Examiner may wish to also consider the relevance of Caprara (US 5,440,510; issued August 8, 1995) and Yoshida (US 4,086,642; issued April 25, 1978). Caprara teaches a protection diode that prevents charging of the MOS transistor’s floating gate during manufacture. Caprara Abstract; col. 2,11. 50-52. The floating gate 10 is covered by a dielectric layer 11 and a control gate 12. Id. col. 4,11. 57-68. The control gate connects to p-n diode 19-4 to prevent the floating gate from becoming charged during manufacturing and causing damage to dielectric layers 9 and 11. Id. col. 5,1. 57- co. 6,1. 5. Yoshida teaches a grounded protective diode circuit that prevents a MOSFET gate from becoming charged up during manufacturing. See e.g., Yoshida FIG. 1. 16 Appeal 2017-003762 Application 13/607,128 CONCLUSION OF LAW We reverse the lack of written description and obviousness rejection in favor of a New Ground of Rejection of the claims for obviousness. All pending, rejected claims fall. Rule 41.50(b) provides that “[a] new ground of rejection pursuant to this paragraph shall not be considered final for judicial review.” Rule 41.50(b) also provides the following: When the Board enters such a non-final decision, the appellant, within two months from the date of the decision, must exercise one of the following two options with respect to the new ground of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. Submit an appropriate amendment of the claims so rejected or new Evidence relating to the claims so rejected, or both, and have the matter reconsidered by the examiner, in which event the prosecution will be remanded to the examiner. The new ground of rejection is binding upon the examiner unless an amendment or new Evidence not previously of Record is made which, in the opinion of the examiner, overcomes the new ground of rejection designated in the decision. Should the examiner reject the claims, appellant may again appeal to the Board pursuant to this subpart. (2) Request rehearing. Request that the proceeding be reheard under § 41.52 by the Board upon the same Record. The request for rehearing must address any new ground of rejection and state with particularity the points believed to have been misapprehended or overlooked in entering the new ground of rejection and also state all other grounds upon which rehearing is sought. 17 Appeal 2017-003762 Application 13/607,128 Further guidance on responding to a new ground of rejection can be found in the Manual of Patent Examining Procedure (MPEP) § 1214.01 (9th Ed., Rev. 9, Nov. 2015). REVERSED and NEW GROUND OF REJECTION UNDER 41.50(b) 18 Copy with citationCopy as parenthetical citation